參數(shù)資料
型號(hào)： XC17128EPD8C
廠(chǎng)商： Xilinx Inc
文件頁(yè)數(shù)： 6/13頁(yè)
文件大?。?/td> 0K
描述： IC PROM SERIAL CONFIG 128K 8-DIP
產(chǎn)品變化通告： XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010
Product Discontinuation 28/Jul/2010
標(biāo)準(zhǔn)包裝： 50
可編程類(lèi)型： OTP
存儲(chǔ)容量： 128kb
電源電壓： 4.75 V ~ 5.25 V
工作溫度： 0°C ~ 70°C
封裝/外殼： 8-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 8-PDIP
包裝： 管件
其它名稱(chēng)： 122-1191
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008
Product Specification
2
R
Pin Description
DATA
Data output is in a high-impedance state when either CE or
OE are inactive. During programming, the DATA pin is I/O.
Note that OE can be programmed to be either active High or
active Low.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The
polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this
document describes the pin as RESET/OE, although the
opposite polarity is possible on all devices. When RESET is
active, the address counter is held at "0", and puts the DATA
output in a high-impedance state. The polarity of this input
is programmable. The default is active High RESET, but the
preferred option is active Low RESET, because it can be
driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer
interface. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have
different methods to invert this pin.
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-ICC standby mode.
CEO
Chip Enable output, to be connected to the CE input of the next
PROM in the daisy chain. This output is Low when the CE and
OE inputs are both active AND the internal address counter
has been incremented beyond its Terminal Count (TC) value.
In other words: when the PROM has been read, CEO follows
CE as long as OE is active. When OE goes inactive, CEO
stays High until the PROM is reset. Note that OE can be
programmed to be either active High or active Low.
VPP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read
operation, this pin must be connected to VCC. Failure to do
so may lead to unpredictable, temperature-dependent
operation and severe problems in circuit debugging. Do not
leave VPP floating!
VCC and GND
Positive supply and ground pins.
PROM Pinouts
Pins not listed are "no connects."
"
Capacity
Pin Name
8-pin
PDIP
(PD8/
PDG8
)
SOIC
(SO8/
SOG8)
VOIC
(VO8/
VOG8)
20-pin
SOIC
(SO20)
20-pin
PLCC
(PC20/
PCG20)
44-pin
VQFP
(VQ44)
44-pin
PLCC
(PC44)
DATA
1
2
40
2
CLK
2
3
4
43
5
RESET/OE
(OE/RESET)
38
6
13
19
CE
4
10
8
15
21
GND
5
11
10
18, 41
24, 3
CEO
6
13
14
21
27
VPP
718
17
35
41
VCC
820
20
38
44
Devices
Configuration Bits
XC1704L
4,194,304
XC1702L
2,097,152
XC1701/L
1,048,576
XC17512L
524,288
XC1736E
36,288
XC1765E/EL
65,536
XC17128E/EL
131,072
XC17256E/EL
262,144
Product Obsolete or Under Obsolescence
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