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    參數(shù)資料
    型號: XC17S150AVO8I
    廠商: Xilinx Inc
    文件頁數(shù): 2/8頁
    文件大?。?/td> 0K
    描述: IC PROM SER 150K 8-SOIC
    標準包裝: 98
    可編程類型: OTP
    存儲容量: 1.5Mb
    電源電壓: 3 V ~ 3.6 V
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
    供應(yīng)商設(shè)備封裝: 8-TSOP
    包裝: 管件
    Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
    DS078 (v1.10) June 25, 2007
    Product Specification
    2
    R
    Pin Description
    Pins not listed are no connects.
    Pinout Diagrams
    Pin Name
    8-pin
    PDIP
    (PD8/PDG8)
    and
    VOIC/TSOP
    (VO8/VOG8)
    20-pin
    SOIC
    (SO20)
    44-pin
    VQFP
    (VQ44)
    Pin Description
    DATA
    1
    40
    Data output, High-Z state when either CE or OE are inactive. During
    programming, the DATA pin is I/O. Note that OE can be programmed to
    be either active High or active Low.
    CLK
    2
    3
    43
    Each rising edge on the CLK input increments the internal address
    counter, if both CE and OE are active.
    RESET/OE
    (OE/RESET)
    38
    13
    When High, this input holds the address counter reset and puts the
    DATA output in a high-impedance state. The polarity of this input pin is
    programmable as either RESET/OE or OE/RESET. To avoid confusion,
    this document describes the pin as RESET/OE, although the opposite
    polarity is possible on all devices. When RESET is active, the address
    counter is held at zero, and the DATA output is in a high-impedance
    state. The polarity of this input is programmable. The default is active-
    High RESET, but the preferred option is active Low RESET, because it
    can be connected to the FPGAs INIT pin and a pull-up resistor.
    The polarity of this pin is controlled in the programmer interface. This
    input pin is easily inverted using the Xilinx HW-130 programmer software.
    Third-party programmers have different methods to invert this pin.
    CE
    410
    15
    When High, this pin resets the internal address counter, puts the DATA
    output in a high-impedance state, and forces the device into low-ICC
    standby mode.
    GND
    5
    11
    18, 41
    GND is the ground connection.
    VCC
    7, 8
    18, 20
    38, 35
    The VCC pins are to be connected to the positive voltage supply.
    PD8/PDG8
    VO8/VOG8
    Top View
    ds078_04_061805
    8
    7
    6
    5
    1
    2
    3
    4
    VCC
    NC
    GND
    DATA (D0)
    CLK
    OE/RESET
    CE
    ds078_05_061805
    SO20
    Top View
    20
    19
    18
    17
    16
    15
    14
    13
    12
    11
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    DATA(D0)
    NC
    CLK
    NC
    OE/RESET
    NC
    CE
    VCC
    NC
    VCC
    NC
    GND
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    VQ44
    Top View
    NC
    OE/RESET
    NC
    CE
    NC
    GND
    NC
    CLK
    NC
    GND
    D
    A
    T
    A(D0)
    NC
    VCC
    NC
    VCC
    NC
    ds073_06_061805
    44
    43
    42
    41
    40
    39
    38
    37
    36
    35
    34
    33
    32
    31
    30
    29
    28
    27
    26
    25
    24
    23
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
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