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參數(shù)資料
| 型號： | XC17S15AVOG8C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SERIAL 15K 8-SOIC |
| 標準包裝： | 98 |
| 可編程類型： | OTP |
| 存儲容量： | 150kb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-TSOP |
| 包裝： | 管件 |
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
DS078 (v1.10) June 25, 2007
Product Specification
3
R
Controlling PROMs
Connecting the Spartan device with the PROM:
The DATA output of the PROM drives the DIN input of
the lead Spartan device.
The Master Spartan device CCLK output drives the
CLK input of the PROM.
The RESET/OE input of the PROM is connected to the
INIT pin of the Spartan device and a pull-up resistor.
This connection assures that the PROM address
counter is reset before the start of any
(re)configuration, even when a reconfiguration is
initiated by a VCC glitch.
The CE input of the PROM is connected to the DONE
pin of the Spartan device and a pull-up resistor. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device mode pins. In Master
Serial mode, the Spartan device automatically loads the
configuration program from an external memory. The
XC17S00A PROM has been designed for compatibility with
the Master Serial mode.
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the mode pins are set
to Master Serial mode. Data is read from the PROM
sequentially on a single data line. Synchronization is
provided by the rising edge of the temporary signal CCLK,
which is generated during configuration.
Master Serial mode provides a simple configuration
interface (Figure 1). Only a serial data line, two control lines,
and a clock line are required to configure the Spartan
device. Data from the PROM is read sequentially, accessed
via the internal address and bit counters which are
incremented on every valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The
Spartan-II/Spartan-IIE family takes care of this
automatically with an on-chip pull-up/down resistor or
keeper circuit.
The one-time-programmable XC17S00A PROM in
Figure 1, page 3 supports automatic loading of
configuration programs. An early DONE inhibits the PROM
data output one CCLK cycle before the Spartan FPGA I/Os
become active.
Figure 1: XC17S00A PROM Connections to FPGA in Master Serial Mode
DIN
CCLK
INIT
DONE
XC17S00A
PROM
DATA
CLK
CE
Spartan-II/
Spartan-IIE
Master Serial
DS078_01_061107
OE/RESET
M0
M1
M2
3.3V
VCC
3.3V
3
.3
K
Ω
Notes:
1. If the DriveDone configuration option is not active, pull up DONE with a 3.3 k
Ω resistor.
3
.3
K
Ω
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