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| 型號： | XC17S200XLSO20I |
| 英文描述： | Peripheral IC |
| 中文描述： | 外圍芯片 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 84K |
| 代理商： | XC17S200XLSO20I |
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
DS030 (v1.7) April 7, 2001
Product Specification
1-800-255-77783
R
address and bit counters which are incremented on every
valid rising edge of CCLK.
If the user-programmable, dual-function D
IN
pin on the
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The Spar-
tan family takes care of this automatically with an on-chip
default pull-up resistor.
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple-configurations for a single Spartan device
are stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and con-
figuration begins with the first program stored in memory.
Since the OE pin is held Low, the address counters are left
unchanged after configuration is complete. Therefore, to
reprogram the FPGA with another program, the DONE line
is pulled Low and configuration begins at the last value of
the address counters.
This method fails if a user applies RESET during the Spar-
tan device configuration process. The Spartan device
aborts the configuration and then restarts a new configura-
tion, as intended, but the PROM does not reset its address
counter, since it never saw a High level on its OE input. The
new configuration, therefore, reads the remaining data in
the PROM and interprets it as preamble, length count etc.
Since the Spartan device is the Master, it issues the neces-
sary number of CCLK pulses, up to 16 million (2
24
) and
DONE goes High. However, the Spartan device configura-
tion will be completely wrong, with potential contentions
inside the Spartan device and on its output pins. This
method must, therefore, never be used when there is any
chance of external reset during configuration.
Figure 1:
Master Serial Mode.
The one-time-programmable Spartan PROM supports automatic loading of configuration programs.
An early DONE inhibits the PROM data output one CCLK cycle before the Spartan FPGA I/Os become active.
D
IN
CCLK
INIT
DONE
Spartan
PROM
DATA
3.3V
CLK
CE
Spartan
Master Serial
(Low Resets the Address Pointer)
DS030_01_040400
CCLK
(Output)
D
IN
D
OUT
(Output)
OE/RESET
MODE
4.7K
V
CC
V
CC
V
PP
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