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參數(shù)資料
| 型號： | XC17S30PD8I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 0K |
| 描述： | IC PROM PROG I-TEMP 5V 8-DIP |
| 產(chǎn)品變化通告： | Product Discontinuation 28/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 可編程類型： | OTP |
| 存儲容量： | 300kb |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
DS030 (v1.12) June 20, 2008
Product Specification
1
Copyright 1998-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
Features
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan, and Spartan-XL FPGAs
Simple interface to the Spartan device requires only
one user I/O pin
Programmable reset polarity (active High or active Low)
Low-power CMOS floating-gate process
Available in 5V and 3.3V versions
Available in compact plastic 8-pin DIP, 8-pin VOIC, or
20-pin SOIC packages
Programming support by leading programmer
manufacturers
Lead-free (RoHS-compliant) packaging available
Design support using the Xilinx Alliance and
Foundation series software packages
Guaranteed 20 year life data retention
Introduction
The Spartan family of PROMs provides an easy-to-use,
cost-effective method for storing Spartan device
configuration bitstreams.
When the Spartan device is in Master Serial mode, it
generates a configuration clock that drives the Spartan
FPGA PROM. A short access time after the rising clock
edge, data appears on the PROM DATA output pin that is
connected to the Spartan device DIN pin. The Spartan
device generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When a Spartan device is in Slave Serial mode, the
PROM and the Spartan device must both be clocked by an
incoming signal.
For device programming, either the Xilinx Alliance or the
Foundation series development systems compiles the
Spartan device design file into a standard HEX format which
is then transferred to most commercial PROM programmers.
X-Ref Target - Figure 0
Spartan/XL Family One-Time Programmable
Configuration PROMs (XC17S00/XL)
DS030 (v1.12) June 20, 2008
Product Specification
R
Spartan FPGA
Configuration Bits
Compatible Spartan PROM
XCS05
53,984
XC17S05
XCS05XL
54,544
XC17S05XL
XCS10
95,008
XC17S10
XCS10XL
95,752
XC17S10XL
XCS20
178,144
XC17S20
XCS20XL
179,160
XC17S20XL
XCS30
247,968
XC17S30
XCS30XL
249,168
XC17S30XL
XCS40
329,312
XC17S40
XCS40XL
330,696
XC17S40XL
XC2S50(1)
559,200
XC17S50XL
XC2S100(1)
781,216
XC17S100XL
XC2S150(1)
1,040,096
XC17S150XL
Notes:
1.
For new Spartan-II FPGA designs, it is recommended to use the 17S00A family.
Product Obsolete or Under Obsolescence
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