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參數(shù)資料
| 型號(hào)： | XC17V02PC44I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 4/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SER 2MBIT 3.3V 44-PLCC |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 14/May/2007 |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 可編程類型： | OTP |
| 存儲(chǔ)容量： | 2Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
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XC17V00 Series Configuration PROMs
DS073 (v2.0) April 7, 2014
Product Specification
12
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
AC Characteristics over Operating Condition for XC17V16 and XC17V08
X-Ref Target - Figure 5
Symbol
Description
Min
Max
Units
TOE
OE to data delay
–
15
ns
TCE
CE to data delay
–
20
ns
TCAC
CLK to data delay(2)
–20
ns
TDF
CE or OE to data float delay(3,4)
–35
ns
TOH
Data hold from CE, OE, or CLK(4)
0–
ns
TCYC
Clock periods
50
–
ns
TLC
CLK Low time(4)
25
–
ns
THC
CLK High time(4)
25
–
ns
TSCE
CE setup time to CLK (to guarantee proper counting)
25
–
ns
THCE
CE hold time to CLK (to guarantee proper counting)
0
–
ns
THOE
OE hold time (guarantees counters are reset)
25
–
ns
TSBUSY
BUSY setup time
5
–
ns
THBUSY
BUSY hold time
5
–
ns
TCEH
CE High time (guarantees counters are reset)
20
–
ns
Notes:
1.
AC test load = 50 pF.
2.
When BUSY = 0.
3.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
4.
Guaranteed by design, not tested.
5.
All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
6.
If TCEH High, 2 μs, TCE = 2 μs.
7.
If THOE High, 2 μs, TOE = 2 μs.
RESET/OE(1)
CE
CLK
BUSY(2)
DATA
TCE
TOE
TLC
TSCE
THCE
THOE
TCAC
TSBUSY
THBUSY
TOH
TDF
TOH
THC
DS073_05_031606
TCYC
TCEH
Note:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high RESET polarity.
Timing specifications are identical for both polarity settings.
2. If BUSY is inactive (Low) during a rising CLK edge, then new DATA appears at time TCAC after the rising CLK edge. If BUSY is active (High)
during a rising CLK edge, then there is no corresponding change to DATA.
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