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參數(shù)資料
| 型號： | XC17V04PC44I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SER 4MBIT 3.3V 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 可編程類型： | OTP |
| 存儲容量： | 4Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
XC17V00 Series Configuration PROMs
DS073 (v2.0) April 7, 2014
Product Specification
11
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
AC Characteristics over Operating Condition for XC17V04, XC17V02, and
XC17V01
X-Ref Target - Figure 4
Symbol
Description
Min
Max
Units
TOE
OE to data delay
–
30
ns
TCE
CE to data delay
–
45
ns
TCAC
CLK to data delay
–
45
ns
TDF
CE or OE to data float delay(2,3)
–50
ns
TOH
Data hold from CE, OE, or CLK(3)
0–
ns
TCYC
Clock periods
67
–
ns
TLC
CLK Low time(3)
25
–
ns
THC
CLK High time(3)
25
–
ns
TSCE
CE setup time to CLK (to guarantee proper counting)
25
–
ns
THCE
CE hold time to CLK (to guarantee proper counting)
0
–
ns
THOE
OE hold time (guarantees counters are reset)
25
–
ns
TCEH
CE High time (guarantees counters are reset)
20
–
ns
Notes:
1.
AC test load = 50 pF.
2.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3.
Guaranteed by design, not tested.
4.
All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5.
If TCEH High, 2 μs, TCE = 2 μs.
6.
If THOE High, 2 μs, TOE = 2 μs.
RESET/OE
CE
CLK
DATA
TCE
TOE
TLC
TSCE
THCE
THOE
TCAC
TOH
TDF
TOH
THC
DS073_04_14102005
TCYC
TCEH
Notes:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high
RESET polarity. Timing specifications are identical for both polarity settings.
2 The diagram shows timing relationships. The diagram is not reflective of actual FPGA signal sequences. See the appropriate
FPGA data sheet or user guide for actual configuration signal sequences.
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