參數(shù)資料
型號(hào)： XC18V01PC20C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 23/24頁(yè)
文件大小： 0K
描述： IC PROM SERIAL CONFIG 1M 20-PLCC
標(biāo)準(zhǔn)包裝： 46
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 1Mb
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
封裝/外殼： 20-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 20-PLCC
包裝： 管件
其它名稱： 122-1236
XC18V01PC20C-ND
XC18V00 Series In-System-Programmable Configuration PROMs
DS026 (v5.2) January 11, 2008
Product Specification
8
R
The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information
about the device’s programmed contents. By using the USERCODE instruction, a user-programmable identification code
can be shifted out for examination. This code is loaded into the USERCODE register during programming of the XC18V00
device. If the device is blank or was not loaded during programming, the USERCODE register contains FFFFFFFFh.
XC18V00 TAP Characteristics
The XC18V00 family performs both in-system programming and IEEE 1149.1 Boundary-Scan (JTAG) testing via a single
four-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform
both functions. The AC characteristics of the XC18V00 TAP are described as follows.
TAP Timing
Figure 4 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both Boundary-
Scan and ISP operations.
TAP AC Parameters
Table 6 shows the timing parameters for the TAP waveforms shown in Figure 4.
X-Ref Target - Figure 4
Figure 4: Test Access Port Timing
Table 6: Test Access Port Timing Parameters
Symbol
Parameter
Min
Max
Units
TCKMIN1
TCK minimum clock period
100
–
ns
TCKMIN2
TCK minimum clock period, Bypass mode
50
–
ns
TMSS
TMS setup time
10
–
ns
TMSH
TMS hold time
25
–
ns
TDIS
TDI setup time
10
–
ns
TDIH
TDI hold time
25
–
ns
TDOV
TDO valid delay
–
25
ns
TCK
TCKMIN1,2
TMSS
TMS
TDI
TDO
TMSH
TDIH
TDOV
TDIS
DS026_04_032702
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