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參數(shù)資料
| 型號： | XC18V02VQG44C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM REPROGR 2MB 44-VQFP |
| 標準包裝： | 160 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲容量： | 2Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-VQFP（10x10） |
| 包裝： | 托盤 |
XC18V00 Series In-System-Programmable Configuration PROMs
DS026 (v5.2) January 11, 2008
Product Specification
13
R
X-Ref Target - Figure 8
Figure 8: Configuring Multiple Devices with Identical Patterns in Master/Slave Serial,
Master/Slave SelectMAP, or Master/Slave Parallel Mode
XC18V00
PROM
First
PROM
(PROM 0)
VCCINT
VCCO
(2)
TDI
TMS
TCK
GND
D[0:7](3)
CLK
CE
CEO
OE/RESET
CF
TDO
Xilinx FPGA
Master
Serial/SelectMAP
Xilinx FPGA
Slave
Serial/SelectMAP
D[0:7]
(3)
CCLK
DONE
INIT_B (INIT)
PROG_B (PROGRAM)
TDI
TMS
TCK
GND
MODE PINS
(1)
TDO
4.7
k
Ω
4.7
k
Ω
(1)
VCCO
(2)
TDI
TMS
TCK
TDO
Notes:
1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide.
2 For compatible voltages, refer to the appropriate data sheet.
3 Serial modes do not require the D[1:7], RDWR_B, or CS_B pins to be connected.
4 External oscillator required if CLK is not supplied by an FPGA in Master mode. Refer to the appropriate FPGA data sheet.
D[0:7]
(3)
CCLK
DONE
INIT_B (INIT)
PROG_B (PROGRAM)
TDI
TMS
TCK
GND
XC18V00
PROM
Cascaded
PROM
(PROM 1)
VCCINT
VCCO
(2)
TDI
TMS
TCK
GND
D[0:7](3)
CLK
CE
CEO
OE/RESET
CF
TDO
MODE PINS
(1)
TDO
DS026_17_111207
RDWR_B
(3)
CS_B
(3)
RDWR_B
(3)
CS_B
(3)
VCCO VCCINT
External (4)
Oscillator
8
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