- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19477 > XC2C256-7FTG256I (Xilinx Inc)IC CR-II CPLD 256MCELL 256FTBGA PDF資料下載
參數(shù)資料
| 型號： | XC2C256-7FTG256I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CR-II CPLD 256MCELL 256FTBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | CoolRunner II |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 6.7ns |
| 電壓電源 - 內(nèi)部： | 1.7 V ~ 1.9 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 256 |
| 門數(shù)： | 6000 |
| 輸入/輸出數(shù)： | 184 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
| 包裝： | 托盤 |
| 配用： | 122-1573-ND - KIT STARTER COOLRUNNER-II LP/LC 122-1512-ND - KIT DESIGN CPLD W/BATT HOLDER |
CoolRunner-II CPLD Family
6
DS090 (v3.1) September 11, 2008
Product Specification
R
software. The AIM minimizes both propagation delay and
power as it makes attachments to the various FBs.
I/O Block
I/O blocks are primarily transceivers. However, each I/O is
either automatically compliant with standard voltage ranges
or can be programmed to become so. See XAPP382 for
detailed information on CoolRunner-II I/Os.
In addition to voltage levels, each input can selectively
arrive through Schmitt-trigger inputs. This adds a small time
delay, but substantially reduces noise on that input pin.
Approximately 500 mV of hysteresis is added when
Schmitt-trigger inputs are selected. All LVCMOS inputs can
have hysteresis input. Hysteresis also allows easy genera-
tion of external clock circuits. The Schmitt-trigger path is
patibility with I/O standards.
Outputs can be directly driven, 3-stated or open-drain con-
figured. A choice of slow or fast slew rate output signal is
also available. Table 5 summarizes various supported volt-
age standards associated with specific part capacities. All
inputs and disabled outputs are voltage tolerant up to 3.3V.
The CoolRunner-II family supports SSTL2-1, SSTL3-1 and
HSTL-1 high-speed I/O standards in the 128-macrocell and
larger devices. Figure 4 details the I/O pin, where it is noted
that the inputs requiring comparison to an external refer-
ence voltage are available. These I/O standards all require
VREF pins for proper operation. The CoolRunner-II CPLD
allows any I/O pin to act as a VREF pin, granting the board
layout engineer extra freedom when laying out the pins.
However, if VREF pin placement is not done properly, addi-
tional VREF pins might be required, resulting in a loss of
potential I/O pins or board re-work. See XAPP399 for
details regarding VREF pins and their placement.
VREF has pin-range requirements that must be observed.
The Xilinx software aids designers in remaining within the
proper pin range.
Table 5 summarizes the single ended I/O standard support
and shows which standards require VREF values and board
termination. VREF detail is given in specific data sheets.
Figure 4: CoolRunner-II CPLD I/O Block Diagram
Enabled
To Macrocell
Direct Input
To AIM
4
CTE
PTB
GTS[0:3]
CGND
Open Drain
From Macrocell
VCCIO
VREF
Disabled
Hysteresis
Available on 128 Macrocell Devices and Larger
Global termination
Pullup/Bus-Hold
DS090_04_121201
Table 5: CoolRunner-II CPLD I/O Standard Summary
IOSTANDARD
Attribute
VCCIO
Input VREF
Board Termination Voltage
(VTT)
Schmitt-trigger Support
LVTTL
3.3
N/A
Optional
LVCMOS33
3.3
N/A
Optional
LVCMOS25
2.5
N/A
Optional
LVCMOS18
1.8
N/A
Optional
LVCMOS15
1.5
N/A
Not optional
HSTL_1
1.5
0.75
Not optional
SSTL2_1
2.5
1.25
Not optional
SSTL3_1
3.3
1.5
Not optional
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LP2980AIBPX-3.3 | IC REG LDO 3.3V 50MA 5MICROSMD |
| DS1631S+ | IC THERMOMETER DIG HI-PREC 8SOIC |
| 171-009-202L031 | CONN DB9 FMALE SOLDER CUP TIN |
| MIC284-1YM | IC SUPERVISOR THERM 2ZONE 8-SOIC |
| V72A3V3E264BL | CONVERTER MOD DC/DC 3.3V 264W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2C256-7PQ208C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 6K GATES 256 MCRCLLS 300MHZ 0.18UM 1.8V 2 - Trays 制造商:Xilinx 功能描述:IC CPLD 256MC 6.7NS 208PQFP 制造商:Xilinx 功能描述:IC CR-II CPLD 256MCELL 208PQFP |
| XC2C256-7PQ208CES | 制造商:Xilinx 功能描述: |
| XC2C256-7PQ208I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 6K GATES 256 MCRCLLS 300MHZ 0.18UM 1.8V 2 - Trays 制造商:Xilinx 功能描述:IC SYSTEM GATE 制造商:Xilinx 功能描述:IC CR-II CPLD 256MCELL 208PQFP 制造商:Xilinx 功能描述:IC CPLD 256MC 6.7NS 208PQFP |
| XC2C256-7PQG208C | 功能描述:IC CRII CPLD 256MCRCELL 208PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner II 標(biāo)準(zhǔn)包裝:90 系列:ispMACH® 4A 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.5ns 電壓電源 - 內(nèi)部:4.75 V ~ 5.25 V 邏輯元件/邏輯塊數(shù)目:- 宏單元數(shù):64 門數(shù):- 輸入/輸出數(shù):48 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 |
| XC2C256-7PQG208I | 功能描述:IC CR-II CPLD 256MCELL 208PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner II 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。