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| 型號(hào)： | XC2C512-10FTG256C |
| 廠(chǎng)商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 14/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CR-II CPLD 512MCELL 256-FBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | CoolRunner II |
| 可編程類(lèi)型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 9.2ns |
| 電壓電源 - 內(nèi)部： | 1.7 V ~ 1.9 V |
| 邏輯元件/邏輯塊數(shù)目： | 32 |
| 宏單元數(shù)： | 512 |
| 門(mén)數(shù)： | 12000 |
| 輸入/輸出數(shù)： | 212 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | 122-1407 |
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CoolRunner-II CPLD Family
DS090 (v3.1) September 11, 2008
Product Specification
R
Output Banking
CPLDs are widely used as voltage interface translators. To
that end, the output pins are grouped in large banks. The
XC2C32A, XC2C64A, XC2C128 and XC2C256 devices
support two output banks. With two, the outputs switch to
one of two selected output voltage levels, unless both banks
are set to the same voltage. The larger parts (384 and 512
macrocell) support four output banks split evenly. They can
support groupings of one, two, three, or four separate output
voltage levels. This kind of flexibility permits easy interfacing
to 3.3V, 2.5V, 1.8V, and 1.5V in a single part.
DataGATE
Low power is the hallmark of CMOS technology. Other
CPLD families use a sense amplifier approach to creating
product terms, which always has a residual current compo-
nent being drawn. This residual current can be several hun-
dred milliamps, making them unusable in portable systems.
CoolRunner-II CPLDs use standard CMOS methods to cre-
ate the CPLD architecture and deliver the corresponding
low current consumption, without doing any special tricks.
However, sometimes designers want to reduce their system
current even more by selectively disabling circuitry not
being used.
The patented DataGATE technology to permits a straight-
forward approach to additional power reduction. Each I/O
pin has a series switch that can block the arrival of free run-
ning signals that are not of interest. Signals that serve no
use might increase power consumption, and can be dis-
abled. Users are free to do their design, then choose sec-
tions to participate in the DataGATE function. DataGATE is
a logic function that drives an assertion rail threaded
through the medium and high-density CoolRunner-II CPLD
parts. Designers can select inputs to be blocked under the
control of the DataGATE function, effectively blocking con-
trolled switching signals so they do not drive internal chip
capacitances. Output signals that do not switch are held by
the bus hold feature. Any set of input pins can be chosen to
participate in the DataGATE function. Figure 5 shows the
familiar CMOS ICC versus switching frequency graph. With
DataGATE, designers can approach zero power, should
they choose to, in their designs.
Figure 6 shows how DataGATE basically works. One I/O pin
drives the DataGATE Assertion Rail. It can have any
desired logic function on it. It can be as simple as mapping
an input pin to the DataGATE function or as complex as a
counter or state machine output driving the DataGATE I/O
pin through a macrocell. When the DataGATE rail is
asserted High, any pass transistor switch attached to it is
blocked. Each pin has the ability to attach to the AIM
through a DataGATE pass transistor, and thus be blocked. A
latch automatically captures the state of the pin when it
becomes blocked. The DataGATE Assertion Rail threads
throughout all possible I/Os, so each can participate if cho-
sen. Note that one macrocell is singled out to drive the rail,
and that macrocell is exposed to the outside world through a
pin, for inspection. If DataGATE is not needed, this pin is an
ordinary I/O.
There are two attributes associated with the DataGATE fea-
ture in CoolRunner-II CPLDs. The first attribute specifies if
an input is affected by DataGATE and the second desig-
nates the DataGATE control signal.
The DataGATE feature is selectable on a per pin basis.
Each input pin that uses DataGATE must be assigned a
DATA_GATE attribute.
The DataGATE assertion rail can be driven from either an
I/O pin or internal logic. The DataGATE enable signal is a
dedicated DGE/I/O pin for each package in CoolRunner-II
CPLDs. Upon implementation, the software recognizes a
design using DataGATE and automatically assigns this I/O
pin to the DataGATE enable control function, DGE. Inter-
Figure 5: CMOS ICC vs. Switching Frequency Curve
DS090_05_101001
ICC
Frequency
0
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| XC2C512-10FTG256I | 功能描述:IC CR-II CPLD 512MCELL 256-FTBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner II 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類(lèi)型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門(mén)數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP（24x24） 包裝:托盤(pán) |
| XC2C512-10PQ208C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 12K GATES 512 MCRCLLS 166MHZ COMM 0.18UM - Trays 制造商:Xilinx 功能描述:IC CRII CPLD 512MCRCELL 208PQFP |
| XC2C512-10PQ208I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 12K GATES 512 MCRCLLS 166MHZ IND 0.18UM 1 - Trays 制造商:Xilinx 功能描述:IC CRII CPLD 512MCRCELL 208PQFP 制造商:Xilinx 功能描述:IC CPLD 512MC 9.2NS 208PQFP |
| XC2C512-10PQG208C | 功能描述:IC CRII CPLD 512MCRCELL 208PQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner II 標(biāo)準(zhǔn)包裝:90 系列:ispMACH® 4A 可編程類(lèi)型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.5ns 電壓電源 - 內(nèi)部:4.75 V ~ 5.25 V 邏輯元件/邏輯塊數(shù)目:- 宏單元數(shù):64 門(mén)數(shù):- 輸入/輸出數(shù):48 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤(pán) |
| XC2C512-10PQG208I | 功能描述:IC CR-II CPLD 512MCRCELL 208PQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner II 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類(lèi)型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門(mén)數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP（24x24） 包裝:托盤(pán) |
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