參數(shù)資料
型號: XC2C512-10FTG256I
廠商: Xilinx Inc
文件頁數(shù): 15/16頁
文件大小: 0K
描述: IC CR-II CPLD 512MCELL 256-FTBGA
標(biāo)準(zhǔn)包裝: 90
系列: CoolRunner II
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 9.2ns
電壓電源 - 內(nèi)部: 1.7 V ~ 1.9 V
邏輯元件/邏輯塊數(shù)目: 32
宏單元數(shù): 512
門數(shù): 12000
輸入/輸出數(shù): 212
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
包裝: 托盤
CoolRunner-II CPLD Family
8
DS090 (v3.1) September 11, 2008
Product Specification
R
nally generated DataGATE control logic can be assigned to
this I/O pin with the BUFG=DATA_GATE attribute.
Global Signals
Global signals, clocks (GCK), sets/resets (GSR), and output
enables (GTS), are designed to strongly resemble each
other. This approach enables design software to make the
best utilization of their capabilities. Each global capability is
supplemented by a corresponding product term version.
Figure 7 shows the common structure of the global signal
trees. The pin input is buffered, then drives multiple internal
global signal traces to deliver low skew and reduce loading
delays. GCK, GSR, and GTS can also be used as general
purpose I/Os if they are not needed as global signals. The
DataGATE assertion rail is also a global signal.
Figure 6: DataGATE Architecture (output drivers not shown)
PLA
MC1
MC2
MC16
DS090_06_111201
PLA
DataGATE Assertion Rail
PLA
AIM
MC1
MC2
MC16
MC1
MC2
MC16
MC1
MC2
MC16
To AIM
Latch
To AIM
Latch
To AIM
Latch
To AIM
Latch
Figure 7: Global Clocks (GCK), Sets/Resets (GSR), and
Output Enables (GTS)
DS090_07_101001
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