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參數資料
| 型號： | XC2C512-7FTG256I |
| 廠商： | Xilinx Inc |
| 文件頁數： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CR-II CPLD 512MC 256FTBGA |
| 標準包裝： | 90 |
| 系列： | CoolRunner II |
| 可編程類型： | 系統(tǒng)內可編程 |
| 最大延遲時間 tpd(1)： | 7.1ns |
| 電壓電源 - 內部： | 1.7 V ~ 1.9 V |
| 邏輯元件/邏輯塊數目： | 32 |
| 宏單元數： | 512 |
| 門數： | 12000 |
| 輸入/輸出數： | 212 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應商設備封裝： | 256-FTBGA |
| 包裝： | 托盤 |
CoolRunner-II CPLD Family
DS090 (v3.1) September 11, 2008
Product Specification
R
Macrocell
The CoolRunner-II CPLD macrocell is extremely efficient
and streamlined for logic creation. Users can develop sum
of product (SOP) logic expressions that comprise up to 40
inputs and span 56 product terms within a single function
block. The macrocell can further combine the SOP expres-
sion into an XOR gate with another single p-term expres-
sion. The resulting logic expression’s polarity is also
selectable. As well, the logic function can be pure combina-
torial or registered, with the storage element operating
selectably as a D or T flip-flop, or transparent latch. Avail-
able at each macrocell are independent selections of global,
function block level or local p-term derived clocks, sets,
resets, and output enables. Each macrocell flip-flop is con-
figurable for either single edge or DualEDGE clocking, pro-
viding either double data rate capability or the ability to
distribute a slower clock (thereby saving power). For single
edge clocking or latching, either clock polarity can be
selected per macrocell. CoolRunner-II CPLD macrocell
dard logic symbols are used except the trapezoidal multi-
plexers have input selection from statically programmed
configuration select lines (not shown). Xilinx application
note XAPP376 gives a detailed explanation of how logic is
created in the CoolRunner-II CPLD family.
When configured as a D-type flip-flop, each macrocell has
an optional clock enable signal permitting state hold while a
clock runs freely. Note that Control Terms (CT) are available
to be shared for key functions within the FB, and are gener-
ally used whenever the exact same logic function would be
repeatedly created at multiple macrocells. The CT product
terms are available for FB clocking (CTC), FB asynchro-
nous set (CTS), FB asynchronous reset (CTR), and FB out-
put enable (CTE).
Any macrocell flip-flop can be configured as an input regis-
ter or latch, which takes in the signal from the macrocell’s
I/O pin, and directly drives the AIM. The macrocell combina-
tional functionality is retained for use as a buried logic node
if needed. FToggle is the maximum clock frequency to which
a T flip-flop can reliably toggle.
Advanced Interconnect Matrix (AIM)
The Advanced Interconnect Matrix is a highly connected
low power rapid switch. The AIM is directed by the software
to deliver up to a set of 40 signals to each FB for the cre-
ation of logic. Results from all FB macrocells, as well as, all
pin inputs circulate back through the AIM for additional con-
nection available to all other FBs as dictated by the design
Figure 3: CoolRunner-II CPLD Macrocell
GCK0
GCK1
GCK2
CTC
PTC
DS090_03_121201
49 P-terms
To PTA, PTB, PTC of
other macrocells
CTC, CTR,
CTS, CTE
From AIM
4 P-terms
PTA
Direct Input
from
I/O Block
Feedback
to AIM
PTB
PTC
PLA OR Term
PTA
CTS
GSR
GND
VCC
R
D/T
CE
CK
FIF
Latch
DualEDGE
Q
S
40
To I/O Block
PTA
CTR
GSR
GND
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