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參數(shù)資料
| 型號： | XC2C64A-7CPG56I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CR-II CPLD 64MCELL 56-CSBGA |
| 標準包裝： | 360 |
| 系列： | CoolRunner II |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 6.7ns |
| 電壓電源 - 內(nèi)部： | 1.7 V ~ 1.9 V |
| 邏輯元件/邏輯塊數(shù)目： | 4 |
| 宏單元數(shù)： | 64 |
| 門數(shù)： | 1500 |
| 輸入/輸出數(shù)： | 45 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-LFBGA，CSPBGA |
| 供應商設備封裝： | 56-CSBGA（6x6） |
| 包裝： | 托盤 |
| 配用： | 122-1536-ND - KIT STARTER SPARTAN-3E 122-1532-ND - KIT DEVELOPMENT SPARTAN 3ADSP |
| 其它名稱： | 122-1706 XC2C64A-7CPG56I-ND |
CoolRunner-II CPLD Family
DS090 (v3.1) September 11, 2008
Product Specification
R
Timing Model
Figure 11 shows the CoolRunner-II CPLD timing model. It
represents one aspect of the overall architecture from a tim-
ing viewpoint. Each little block is a time delay that a signal
incurs if the signal passes through such a resource. Timing
reports are created by tallying the incremental signal delays
as signals progress within the CPLD. Software creates the
timing reports after a design has been mapped onto the
specific part, and knows the specific delay values for a given
speed grade. Equations for the higher level timing values
the individual parameters and provides a brief definition of
their associated functions. Xilinx application note XAPP375
details the CoolRunner-II CPLD family timing with several
examples.
Figure 11: CoolRunner-II CPLD Timing Model
Note: Always refer to the timing report in ISE Software for accurate timing values for paths.
D/T
S/R
TF
TSUI THI
TCOI
TAOI
TECSU
TECHO
TOUT
TSLEW
TEN
XAPP375_03_010303
TOEM
TPDI
TLOGI2
TLOGI1
TIN
THYS
CE
TDIN
THYS
TCT
TGCK
THYS
TGSR
THYS
TGTS
THYS
Table 6: Timing Parameter Definitions
Symbol
Parameter
Buffer Delays
TlN
Input Buffer Delay
TDIN
Direct data register input delay
TGCK
Global clock (GCK) buffer delay
TGSR
Global set/reset (GSR) buffer delay
TGTS
Global output enable (GTS) buffer delay
TOUT
Output buffer delay
TEN
Output buffer enable/disable delay
TSLEW
Output buffer slew rate control delay
P-term Delays
TCT
Control Term delay (single PT or FB-CT)
TLOGI1
Single P-term logic delay
TLOGI2
Multiple P-term logic delay adder
Macrocell Delays
TPDI
Macrocell input to output valid
TSUI
Macro register setup before clock
THI
Macro register hold after clock
TECSU
Macro register enable clock setup time
TECHO
Macro register enable clock hold time
TCOI
Macro register clock to output valid
TAOI
Macro register set/reset to output valid
THYS
Hysteresis selection delay adder
Feedback Delays
TF
Feedback delay
TOEM
Macrocell to Global OE delay
Table 6: Timing Parameter Definitions (Continued)
Symbol
Parameter
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC2C64A-7CPG56I4124 | 制造商:Xilinx 功能描述: |
| XC2C64A-7PC44C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
| XC2C64A-7PC44I | 制造商:Xilinx 功能描述: |
| XC2C64A-7PCG44C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
| XC2C64A-7PCG44I | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
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