參數(shù)資料
型號(hào)： XC2S100-6FG456C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 14/99頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 2.5V C-TEMP 456-FBGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-II
LAB/CLB數(shù)： 600
邏輯元件/單元數(shù)： 2700
RAM 位總計(jì)： 40960
輸入/輸出數(shù)： 196
門數(shù)： 100000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 456-BBGA
供應(yīng)商設(shè)備封裝： 456-FBGA
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
21
R
Slave Serial Mode
In Slave Serial mode, the FPGA’s CCLK pin is driven by an
external source, allowing FPGAs to be configured from
other logic devices such as microprocessors or in a
daisy-chain configuration. Figure 15 shows connections for
a Master Serial FPGA configuring a Slave Serial FPGA
from a PROM. A Spartan-II device in slave serial mode
should be connected as shown for the third device from the
left. Slave Serial mode is selected by a <11x> on the mode
pins (M0, M1, M2).
Figure 16 shows the timing for Slave Serial configuration.
The serial bitstream must be setup at the DIN input pin a
short time before each rising edge of an externally
generated CCLK.
Multiple FPGAs in Slave Serial mode can be daisy-chained
for configuration from a single source. The maximum
amount of data that can be sent to the DOUT pin for a serial
daisy chain is 220-1 (1,048,575) 32-bit words, or 33,554,400
bits, which is approximately 25 XC2S200 bitstreams. The
configuration bitstream of downstream devices is limited to
this size.
After an FPGA is configured, data for the next device is
routed to the DOUT pin. Data on the DOUT pin changes on
the rising edge of CCLK. Configuration must be delayed
until INIT pins of all daisy-chained FPGAs are High. For
more information, see "Start-up," page 19.
Notes:
1.
If the DriveDone configuration option is not active for any of the FPGAs, pull up DONE with a 330
Ω resistor.
Figure 15: Master/Slave Serial Configuration Circuit Diagram
Spartan-II
(Master Serial)
PROM
PROGRAM
M2
M0 M1
DOUT
CCLK
CLK
3.3V
DATA
CE
CEO
RESET/OE
DIN
INIT
DONE
PROGRAM
3.3 K
DS001_15_060608
GND
Vcc
3.3V
VCCO
VCCINT
2.5V
3.3V
2.5V
Spartan-II
(Slave)
DONE
INIT
PROGRAM
CCLK
DIN
DOUT
M2
M0 M1
GND
VCCO
VCCINT
相關(guān)PDF資料
PDF描述
XC5210-6TQ144C IC FPGA 324 CLB'S 144-TQFP
AMC36DRYI CONN EDGECARD 72POS .100 DIP SLD
XC3064L-8TQ144C IC FPGA 3.3V C-TEMP 144-TQFP
XC3042L-8VQ100I IC FPGA 3.3V I-TEMP 100-VQFP
AMM30DTKT-S288 CONN EDGECARD 60POS .156 EXTEND
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S100-6FG456I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
XC2S100-6FGG256C 制造商:Xilinx 功能描述:XLXXC2S100-6FGG256C IC SYSTEM GATE 制造商:Xilinx 功能描述:FPGA SPARTAN-II 100K GATES 2700 CELLS 263MHZ 2.5V 256FBGA - Trays
XC2S100-6FGG256I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
XC2S100-6FGG456C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
XC2S100-6FGG456I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*