- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4288 > XC2S100E-6PQG208C (Xilinx Inc)IC FPGA 1.8V 600 CLB'S 208-PQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | XC2S100E-6PQG208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 16/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V 600 CLB'S 208-PQFP |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Spartan®-IIE |
| LAB/CLB數(shù)： | 600 |
| 邏輯元件/單元數(shù)： | 2700 |
| RAM 位總計(jì)： | 40960 |
| 輸入/輸出數(shù)： | 146 |
| 門數(shù)： | 100000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁
DS077-2 (v3.0) August 9, 2013
15
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Each CLB has four direct feedthrough paths, one per LC.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
Arithmetic Logic
Dedicated carry logic provides capability for high-speed
arithmetic functions. The Spartan-IIE FPGA CLB supports
two separate carry chains, one per slice. The height of the
carry chains is two bits per CLB.
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementations.
The dedicated carry path can also be used to cascade func-
tion generators for implementing wide logic functions.
BUFTs
Each Spartan-IIE FPGA CLB contains two 3-state drivers
(BUFTs) that can drive on-chip busses. The IOBs on the left
and right sides can also drive the on-chip busses. See Ded-
icated Routing, page 17. Each Spartan-IIE FPGA BUFT
has an independent 3-state control pin and an independent
input pin. The 3-state control pin is an active-Low enable
(T). When all BUFTs on a net are disabled, the net is High.
There is no need to instantiate a pull-up unless desired for
simulation purposes. Simultaneously driving BUFTs onto
the same net will not cause contention. If driven both High
and Low, the net will be Low.
Block RAM
Spartan-IIE FPGAs incorporate several large block RAM
memories.
These
complement
the
distributed
RAM
Look-Up Tables (LUTs) that provide shallow memory struc-
tures implemented in CLBs.
Block RAM memory blocks are organized in columns. Most
Spartan-IIE devices contain two such columns, one along
each vertical edge. The XC2S400E has four block RAM col-
umns and the XC2S600E has six block RAM columns.
These columns extend the full height of the chip. Each
memory block is four CLBs high, and consequently, a
Spartan-IIE device 16 CLBs high will contain four memory
blocks per column, and a total of eight blocks.
Each block RAM cell, as illustrated in Figure 8, is a fully syn-
chronous dual-ported 4096-bit RAM with independent con-
trol signals for each port. The data widths of the two ports
can
be
configured
independently,
providing
built-in
bus-width conversion.
Figure 7: F5 and F6 Multiplexers
LUT
DS077-2_05-111501
LUT
MUXF5
MUXF6
LUT
Slice
CLB
LUT
MUXF5
Table 6: Spartan-IIE Block RAM Amounts
Spartan-IIE
Device
# of Blocks
Total Block RAM
Bits
XC2S50E
8
32K
XC2S100E
10
40K
XC2S150E
12
48K
XC2S200E
14
56K
XC2S300E
16
64K
XC2S400E
40
160K
XC2S600E
72
288K
Figure 8: Dual-Port Block RAM
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
WEA
ENA
RSTA
CLKA
ADD[#:0]
DIA[#:0]
DOA[#:0]
DOB[#:0]
RAMB4_S#_S#
DS001_05_060100
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC2S100E-6PQ208C | IC FPGA 1.8V 600 CLB'S 208-PQFP |
| XC6SLX9-3FT256I | IC FPGA SPARTAN 6 256FTGBGA |
| 93LC86C-I/SNG | IC EEPROM 16KBIT 3MHZ 8SOIC |
| XC6SLX9-3FTG256I | IC FPAG SPARTAN 6 9K 256FTGBGA |
| HMC40DRAS | CONN EDGECARD 80POS R/A .100 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S100E-6PQG208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S100E-6TQ144C | 功能描述:IC FPGA 1.8V 600 CLB'S 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC2S100E-6TQ144C0776 | 制造商:Xilinx 功能描述: |
| XC2S100E-6TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
| XC2S100E-6TQG144C | 功能描述:IC FPGA 1.8V 600 CLB'S 144-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。