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參數資料
| 型號： | XC2S400E-6FG456C |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數： | 10/21頁 |
| 文件大?。?/td> | 183K |
| 代理商： | XC2S400E-6FG456C |
Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics
10
www.xilinx.com
1-800-255-7778
DS077-3 (v2.0) November 18, 2002
Product Specification
R
IOB Output Delay Adjustments for Different Standards(1)
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.
Symbol
Description
Standard
Speed Grade
-7
Units
-6
Output Delay Adjustments (Adj)
T
OLVTTL_S2
T
OLVTTL_S4
T
OLVTTL_S6
T
OLVTTL_S8
T
OLVTTL_S12
T
OLVTTL_S16
T
OLVTTL_S24
T
OLVTTL_F2
T
OLVTTL_F4
T
OLVTTL_F6
T
OLVTTL_F8
T
OLVTTL_F12
T
OLVTTL_F16
T
OLVTTL_F24
T
OLVCMOS2
T
OLVCMOS18
T
OLVDS
T
OLVPECL
T
OPCI33_3
T
OPCI66_3
T
OGTL
T
OGTLP
T
OHSTL_I
T
OHSTL_III
T
OHSTL_IV
T
OSSTL2_I
T
OSSLT2_II
T
OSSTL3_I
T
OSSTL3_II
T
OCTT
T
OAGP
Notes:
1.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the
tables
Constants for Calculating T
IOOP
and
Delay Measurement Methodology
, page 11
.
Standard-specific adjustments for
output delays terminating at pads
(based on standard capacitive
load, C
SL
)
LVTTL, Slow, 2 mA
14.7
7.5
4.8
3.0
1.9
1.7
1.3
13.1
5.3
3.1
1.0
0
–
0.05
–
0.20
0.09
0.7
–
1.2
–
0.41
2.3
–
0.41
0.49
0.8
–
0.51
–
0.91
–
1.01
–
0.51
–
0.91
–
0.51
–
1.01
–
0.61
–
0.91
14.7
7.5
4.8
3.0
1.9
1.7
1.3
13.1
5.3
3.1
1.0
0
–
0.05
–
0.20
0.09
0.7
–
1.2
–
0.41
2.3
–
0.41
0.49
0.8
–
0.51
–
0.91
–
1.01
–
0.51
–
0.91
–
0.51
–
1.01
–
0.61
–
0.91
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVTTL, Fast, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVCMOS2
LVCMOS18
LVDS
LVPECL
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
GTL
GTL+
HSTL I
HSTL III
HSTL IV
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
CTT
AGP
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| XC2S400E-6FGG456C | 功能描述:IC SPARTAN-IIE FPGA 400K 456FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-IIE 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數:4080 邏輯元件/單元數:52224 RAM 位總計:4866048 輸入/輸出數:480 門數:- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC2S400E-6FGG456I | 制造商:Xilinx 功能描述:FPGA SPARTAN-IIE 400K GATES 10800 CELLS 357MHZ 1.8V 456FBGA - Trays |
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