參數(shù)資料
型號(hào)： XC2S400E-6FG676C
英文描述： FPGA
中文描述： FPGA的
文件頁(yè)數(shù)： 11/21頁(yè)
文件大?。?/td> 183K
代理商： XC2S400E-6FG676C
Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics
DS077-3 (v2.0) November 18, 2002
Product Specification
www.xilinx.com
1-800-255-7778
11
R
Calculation of T
IOOP
as a Function of
Capacitance
T
IOOP
is the propagation delay from the O Input of the IOB
to the pad. The values for T
IOOP
are based on the standard
capacitive load (C
SL
) for each I/O standard as listed in the
table
Constants for Calculating T
IOOP
, below.
For other capacitive loads, use the formulas below to calcu-
late an adjusted propagation delay, T
IOOP1
.
T
IOOP1
= T
IOOP
+ Adj + (C
LOAD
–
C
SL
) * F
L
Where:
Adj
is selected from
IOB Output Delay
Adjustments for Different Standards(1)
,
page 10
, according to the I/O standard used
C
LOAD
is the capacitive load for the design
F
L
is the capacitance scaling factor
Delay Measurement Methodology
Standard
V
L(1)
0
V
H(1)
3
Meas.
Point
V
REF
Typ
(2)
LVTTL
1.4
-
LVCMOS2
0
2.5
1.125
-
PCI33_3
Per PCI Spec
-
PCI66_3
Per PCI Spec
-
GTL
V
REF
–
0.2
V
REF
–
0.2
V
REF
–
0.5
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.5
V
REF
+ 0.5
V
REF
+ 0.5
V
REF
+ 1.0
V
REF
V
REF
V
REF
V
REF
V
REF
V
REF
V
REF
V
REF
V
REF
0.80
GTL+
1.0
HSTL Class I
0.75
HSTL Class III V
REF
–
0.5
HSTL Class IV V
REF
–
0.5
SSTL3 I and II V
REF
–
1.0
SSTL2 I and II V
REF
–
0.75 V
REF
+ 0.75
CTT
V
REF
–
0.2
AGP
V
REF
–
(0.2xV
CCO
)
LVDS
1.2
–
0.125 1.2 + 0.125
0.90
0.90
1.5
1.25
V
REF
+ 0.2
V
REF
+
(0.2xV
CCO
)
1.5
Per AGP
Spec
1.2
LVPECL
1.6
–
0.3
1.6 + 0.3
1.6
Notes:
1.
2.
Input waveform switches between V
L
and V
H
.
Measurements are made at V
Typ, Maximum, and
Minimum. Worst-case values are reported.
I/O parameter measurements are made with the capacitance
values shown in the following table,
Constants for
Calculating T
XAPP179
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