參數(shù)資料
型號(hào)： XC2S600E-6FG456I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 4/21頁
文件大?。?/td> 183K
代理商： XC2S600E-6FG456I
Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics
4
www.xilinx.com
1-800-255-7778
DS077-3 (v2.0) November 18, 2002
Product Specification
R
LVDS DC Specifications
LVPECL DC Specifications
These values are valid at the output of the source termina-
tion pack shown under LVPECL, with a 100
differential
load only. The V
OH
levels are 200 mV below standard
LVPECL levels and are compatible with devices tolerant of
lower common-mode ranges. The following table summa-
rizes the DC output specifications of LVPECL.
Symbol
Description
Conditions
Min
Typ
Max
Units
V
CCO
V
OH
V
OL
V
ODIFF
Supply voltage
2.375
2.5
2.625
V
Output High voltage for Q and Q
R
T
= 100
across Q and Q signals
R
T
= 100
across Q and Q signals
R
T
= 100
across Q and Q signals
1.25
1.425
1.6
V
Output Low voltage for Q and Q
0.9
1.075
1.25
V
Differential output voltage (Q
–
Q),
Q = High or (Q
–
Q), Q = High
250
350
450
mV
V
OCM
V
IDIFF
Output common-mode voltage
R
T
= 100
across Q and Q signals
Common-mode input voltage = 1.25 V
1.125
1.25
1.375
V
Differential input voltage (Q
–
Q),
Q = High or (Q
–
Q), Q = High
100
350
-
mV
V
ICM
Input common-mode voltage
Differential input voltage =
±
350 mV
0.2
1.25
2.2
V
Notes:
1.
XAPP179
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