Virtex-II Platform FPGAs: DC and Switching Characteristics
R
DS031-3 (v3.5) November 5, 2007
Module 3 of 4
Product Specification
12
LVDCI, 3.3V, Half-Impedance
LVDCI_DV2_33
TILVDCI_DV2_33
0.00
ns
LVDCI, 2.5V, Half-Impedance
LVDCI_DV2_25
TILVDCI_DV2_25
0.11
0.12
ns
LVDCI, 1.8V, Half-Impedance
LVDCI_DV2_18
TILVDCI_DV2_18
0.42
0.43
0.49
ns
LVDCI, 1.5V, Half-Impedance
LVDCI_DV2_15
TILVDCI_DV2_15
0.98
1.00
1.14
ns
HSLVDCI (High-Speed Low-Voltage DCI), 1.5V
HSLVDCI_15
TIHSLVDCI_15
0.42
0.48
ns
HSLVDCI, 1.8V
HSLVDCI_18
TIHSLVDCI_18
0.52
0.53
0.60
ns
HSLVDCI, 2.5V
HSLVDCI_25
TIHSLVDCI_25
0.42
0.48
ns
HSLVDCI, 3.3V
HSLVDCI_33
TIHSLVDCI_33
0.42
0.48
ns
GTL (Gunning Transceiver Logic) with DCI
GTL_DCI
TIGTL_DCI
0.42
0.48
ns
GTL Plus with DCI
GTLP_DCI
TIGTLP_DCI
0.42
0.48
ns
HSTL (High-Speed Transceiver Logic), Class I, with DCI
HSTL_I_DCI
TIHSTL_I_DCI
0.42
0.48
ns
HSTL, Class II, with DCI
HSTL_II_DCI
TIHSTL_II_DCI
0.42
0.48
ns
HSTL, Class III, with DCI
HSTL_III_DCI
TIHSTL_III_DCI
0.42
0.48
ns
HSTL, Class IV, with DCI
HSTL_IV_DCI
TIHSTL_IV_DCI
0.42
0.48
ns
HSTL, Class I, 1.8V, with DCI
HSTL_I_DCI_18
TIHSTL_I_DCI_18
0.42
0.48
ns
HSTL, Class II, 1.8V, with DCI
HSTL_II_DCI_18
TIHSTL_II_DCI_18
0.42
0.48
ns
HSTL, Class III, 1.8V, with DCI
HSTL_III_DCI_18
TIHSTL_III_DCI_18
0.42
0.48
ns
HSTL, Class IV, 1.8V, with DCI
HSTL_IV_DCI_18
TIHSTL_IV_DCI_18
0.42
0.48
ns
SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI
SSTL18_I_DCI
TISSTL18_I_DCI
0.42
0.48
ns
SSTL, Class II, 1.8V, with DCI
SSTL18_II_DCI
TISSTL18_II_DCI
0.42
0.48
ns
SSTL, Class I, 2.5V, with DCI
SSTL2_I_DCI
TISSTL2_I_DCI
0.42
0.48
ns
SSTL, Class II, 2.5V, with DCI
SSTL2_II_DCI
TISSTL2_II_DCI
0.42
0.48
ns
SSTL, Class I, 3.3V, with DCI
SSTL3_I_DCI
TISSTL3_I_DCI
0.35
0.40
ns
SSTL, Class II, 3.3V, with DCI
SSTL3_II_DCI
TISSTL3_II_DCI
0.35
0.40
ns
LVDS (Low-Voltage Differential Signaling), 2.5V, with DCI
LVDS_25_DCI
TILVDS_25_DCI
0.60
0.69
ns
LVDS, 3.3V, with DCI
LVDS_33_DCI
TILVDS_33_DCI
0.60
0.69
ns
LVDSEXT (LVDS Extended Mode), 2.5V, with DCI
LVDSEXT_25_DCI
TILVDSEXT_25_DCI
0.58
0.59
0.79
ns
LVDSEXT, 3.3V, with DCI
LVDSEXT_33_DCI
TILVDSEXT_33_DCI
0.56
0.65
ns
Notes:
1.
Input timing for LVTTL is measured at 1.4V. For other I/O standards, see
Table 18.
Table 15: IOB Input Switching Characteristics Standard Adjustments (Continued)
Description
IOSTANDARD
Attribute
Timing
Parameter
Speed Grade
Units
-6
-5
-4