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| 型號： | XC3000LSERIES |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 20/76頁 |
| 文件大?。?/td> | 731K |
| 代理商： | XC3000LSERIES |
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R
November 9, 1998 (Version 3.1)
7-29
XC3000 Series Field Programmable Gate Arrays
7
Peripheral Mode
Peripheral mode uses the trailing edge of the logic AND
condition of the CS0, CS1, CS2, and WS inputs to accept
byte-wide data from a microprocessor bus. In the lead
FPGA, this data is loaded into a double-buffered UART-like
parallel-to-serial converter and is serially shifted into the
internal logic. The lead FPGA presents the preamble data
(and all data that overflows the lead device) on the DOUT
pin.
The Ready/Busy output from the lead device acts as a
handshake signal to the microprocessor. RDY/BUSY goes
Low when a byte has been received, and goes High again
when the byte-wide input buffer has transferred its informa-
tion into the shift register, and the buffer is ready to receive
new data. The length of the BUSY signal depends on the
activity in the UART. If the shift register had been empty
when the new byte was received, the BUSY signal lasts for
only two CCLK periods. If the shift register was still full
when the new byte was received, the BUSY signal can be
as long as nine CCLK periods.
Note that after the last byte has been entered, only seven
of its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
X5991
ADDRESS
BUS
DATA
BUS
D0–7
ADDRESS
DECODE
LOGIC
CS0
...
RDY/BUSY
WS
RESET
...
OTHER
I/O PINS
D0–7
CCLK
DOUT
M2
HDC
LDC
FPGA
GENERAL-
PURPOSE
USER I/O
PINS
D/P
M0
M1 PWR
DWN
+5 V
CS2
CS1
CONTROL
SIGNALS
8
INIT
REPROGRAM
+5 V
5 k
*
IF READBACK IS
ACTIVATED, A
5-k
RESISTOR IS
REQUIRED IN SERIES
WITH M1
*
OPTIONAL
DAISY-CHAINED
FPGAs WITH DIFFERENT
CONFIGURATIONS
OC
Figure 27: Peripheral Mode Circuit Diagram
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