1. At power-up, VCC" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� XC3064A-7PC84C
寤犲晢锛� Xilinx Inc
鏂囦欢闋佹暩(sh霉)锛� 17/76闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC LOGIC CL ARRAY 6400GAT 84PLCC
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Product Discontinuation 27/Apr/2010
妯欐簴鍖呰锛� 1
绯诲垪锛� XC3000A/L
LAB/CLB鏁�(sh霉)锛� 224
RAM 浣嶇附瑷堬細 46064
杓稿叆/杓稿嚭鏁�(sh霉)锛� 70
闁€鏁�(sh霉)锛� 4500
闆绘簮闆诲锛� 4.75 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 84-LCC锛圝 褰㈠紩绶氾級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 84-PLCC
鍏跺畠鍚嶇ū锛� 122-1029
R
XC3000 Series Field Programmable Gate Arrays
7-26
November 9, 1998 (Version 3.1)
Notes:
1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
non-monotonically rising VCC may require >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P
after VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
3. Master-serial-mode timing is based on slave-mode testing.
Figure 24: Master Serial Mode Programming Switching Characteristics
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
1
TDSCK
2
TCKDS
n
n + 1
n + 2
n 鈥� 3
n 鈥� 2
n 鈥� 1
n
X3223
Description
Symbol
Min
Max
Units
CCLK
Data In setup
1
TDSCK
60
ns
Data In hold
2
CKDS
0ns
Product Obsolete or Under Obsolescence
鐩搁棞(gu膩n)PDF璩囨枡
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XC3064A-7PQ160C IC LOGIC CL ARRAY 6400GAT 160PQF
ASC49DRYH-S93 CONN EDGECARD 98POS DIP .100 SLD
AMC44DRTI-S13 CONN EDGECARD 88POS .100 EXTEND
AMC44DREI-S13 CONN EDGECARD 88POS .100 EXTEND
FMC18DRES CONN EDGECARD 36POS .100 EYELET
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