參數(shù)資料
型號(hào)： XC3130A-3PQ100C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 20/76頁(yè)
文件大小： 0K
描述： IC LOGIC CL ARRAY 3000GAT 100PQF
產(chǎn)品變化通告： XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
標(biāo)準(zhǔn)包裝： 66
系列： XC3000A/L
LAB/CLB數(shù)： 100
RAM 位總計(jì)： 22176
輸入/輸出數(shù)： 80
門數(shù)： 2000
電源電壓： 4.25 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
其它名稱： 122-1041
R
November 9, 1998 (Version 3.1)
7-29
XC3000 Series Field Programmable Gate Arrays
7
Peripheral Mode
Peripheral mode uses the trailing edge of the logic AND
condition of the CS0, CS1, CS2, and WS inputs to accept
byte-wide data from a microprocessor bus. In the lead
FPGA, this data is loaded into a double-buffered UART-like
parallel-to-serial converter and is serially shifted into the
internal logic. The lead FPGA presents the preamble data
(and all data that overflows the lead device) on the DOUT
pin.
The Ready/Busy output from the lead device acts as a
handshake signal to the microprocessor. RDY/BUSY goes
Low when a byte has been received, and goes High again
when the byte-wide input buffer has transferred its informa-
tion into the shift register, and the buffer is ready to receive
new data. The length of the BUSY signal depends on the
activity in the UART. If the shift register had been empty
when the new byte was received, the BUSY signal lasts for
only two CCLK periods. If the shift register was still full
when the new byte was received, the BUSY signal can be
as long as nine CCLK periods.
Note that after the last byte has been entered, only seven
of its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
X5991
ADDRESS
BUS
DATA
BUS
D0–7
ADDRESS
DECODE
LOGIC
CS0
...
RDY/BUSY
WS
RESET
...
OTHER
I/O PINS
D0–7
CCLK
DOUT
M2
HDC
LDC
FPGA
GENERAL-
PURPOSE
USER I/O
PINS
D/P
M0
M1 PWR
DWN
+5 V
CS2
CS1
CONTROL
SIGNALS
8
INIT
REPROGRAM
+5 V
5 k
*
IF READBACK IS
ACTIVATED, A
5-k
RESISTOR IS
REQUIRED IN SERIES
WITH M1
*
OPTIONAL
DAISY-CHAINED
FPGAs WITH DIFFERENT
CONFIGURATIONS
OC
Figure 27: Peripheral Mode Circuit Diagram
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
XC3130A-3PC84C IC LOGIC CL ARRAY 3000GAT 84PLCC
RCB108DHBR CONN EDGECARD 216PS R/A .050 DIP
XC3120A-3PC68C IC LOGIC CL ARRAY 2000GAT 68PLCC
ASC49DRYN-S93 CONN EDGECARD 98POS DIP .100 SLD
XC3090A-7PC84C IC LOGIC CL ARRAY 9000GAT 84PLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3130A-3PQ100C0262 制造商:Xilinx 功能描述:
XC3130A-3PQ100I 制造商:Xilinx 功能描述:
XC3130A-3VQ100C 制造商:Xilinx 功能描述:
XC3130A-3VQ100I 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3130A-3VQ64C 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*