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參數(shù)資料
| 型號： | XC3S1500-5FGG676C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 54/272頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 1.5M 676-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 3328 |
| 邏輯元件/單元數(shù)： | 29952 |
| RAM 位總計(jì)： | 589824 |
| 輸入/輸出數(shù)： | 487 |
| 門數(shù)： | 1500000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
| 配用： | NANO-SPARTAN-ND - KIT NANOBOARD AND SPARTAN3 DC 807-1001-ND - DAUGHTER CARD XILINX SPARTAN 3 |
Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013
Product Specification
147
PQ208: 208-lead Plastic Quad Flat Pack
The 208-lead plastic quad flat package, PQ208, supports three different Spartan-3 devices, including the XC3S50, the
XC3S200, and the XC3S400. The footprints for the XC3S200 and XC3S400 are identical, as shown in Table 93 and
Figure 47. The XC3S50, however, has fewer I/O pins resulting in 17 unconnected pins on the PQ208 package, labeled as
“N.C.” In Table 93 and Figure 47, these unconnected pins are indicated with a black diamond symbol (
).
All the package pins appear in Table 93 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S50 pinout and the pinout for the XC3S200 and XC3S400, then that difference is
highlighted in Table 93. If the table entry is shaded grey, then there is an unconnected pin on the XC3S50 that maps to a
user-I/O pin on the XC3S200 and XC3S400. If the table entry is shaded tan, then the unconnected pin on the XC3S50 maps
to a VREF-type pin on the XC3S200 and XC3S400. If the other VREF pins in the bank all connect to a voltage reference to
support a special I/O standard, then also connect the N.C. pin on the XC3S50 to the same VREF voltage. This provides
maximum flexibility as you could potentially migrate a design from the XC3S50 device to an XC3S200 or XC3S400 FPGA
without changing the printed circuit board.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
Pinout Table
Table 93: PQ208 Package Pinout
Bank
XC3S50
Pin Name
XC3S200, XC3S400
Pin Names
PQ208 Pin
Number
Type
0
IO
P189
I/O
0
IO
P197
I/O
0
N.C. (
)
IO/VREF_0
P200
VREF
0
IO/VREF_0
P205
VREF
0
IO_L01N_0/VRP_0
P204
DCI
0
IO_L01P_0/VRN_0
P203
DCI
0
IO_L25N_0
P199
I/O
0
IO_L25P_0
P198
I/O
0
IO_L27N_0
P196
I/O
0
IO_L27P_0
P194
I/O
0
IO_L30N_0
P191
I/O
0
IO_L30P_0
P190
I/O
0
IO_L31N_0
P187
I/O
0
IO_L31P_0/VREF_0
P185
VREF
0
IO_L32N_0/GCLK7
P184
GCLK
0
IO_L32P_0/GCLK6
P183
GCLK
0
VCCO_0
P188
VCCO
0
VCCO_0
P201
VCCO
1
IO
P167
I/O
1
IO
P175
I/O
1
IO
P182
I/O
1
IO_L01N_1/VRP_1
P162
DCI
1
IO_L01P_1/VRN_1
P161
DCI
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