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| 型號： | XC4003E-3PC84I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 67/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA I-TEMP 5V 3-SPD 84-PLCC |
| 產(chǎn)品變化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 100 |
| 邏輯元件/單元數(shù)： | 238 |
| RAM 位總計： | 3200 |
| 輸入/輸出數(shù)： | 61 |
| 門數(shù)： | 3000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC |
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-12
May 14, 1999 (Version 1.6)
Supported CLB memory congurations and timing modes
for single- and dual-port modes are shown in Table 3.
XC4000 Series devices are the rst programmable logic
devices with edge-triggered (synchronous) and dual-port
RAM accessible to the user.
Edge-triggered RAM simpli-
es system timing. Dual-port RAM doubles the effective
throughput of FIFO applications. These features can be
individually programmed in any XC4000 Series CLB.
Advantages of On-Chip and Edge-Triggered RAM
The on-chip RAM is extremely fast. The read access time is
the same as the logic delay.
The write access time is
slightly slower.
Both access times are much faster than
any off-chip solution, because they avoid I/O delays.
Edge-triggered RAM, also called synchronous RAM, is a
feature never before available in a Field Programmable
Gate Array. The simplicity of designing with edge-triggered
RAM, and the markedly higher achievable performance,
add up to a signicant improvement over existing devices
with on-chip RAM.
Three application notes are available from Xilinx that dis-
cuss edge-triggered RAM: “
XC4000E Edge-Triggered and
Dual-Port
RAM
Capability,”“Implementing
FIFOs
in
XC4000E RAM,” and “Synchronous and Asynchronous
FIFO Designs.” All three application notes apply to both
XC4000E and XC4000X RAM.
RAM Conguration Options
The function generators in any CLB can be congured as
RAM arrays in the following sizes:
Two 16x1 RAMs: two data inputs and two data outputs
with identical or, if preferred, different addressing for
each RAM
One 32x1 RAM: one data input and one data output.
One F or G function generator can be congured as a 16x1
RAM while the other function generators are used to imple-
ment any function of up to 5 inputs.
Additionally, the XC4000 Series RAM may have either of
two timing modes:
Edge-Triggered (Synchronous): data written by the
designated edge of the CLB clock. WE acts as a true
clock enable.
Level-Sensitive (Asynchronous): an external WE signal
acts as the write strobe.
The selected timing mode applies to both function genera-
tors within a CLB when both are congured as RAM.
The number of read ports is also programmable:
Single Port: each function generator has a common
read and write port
Dual Port: both function generators are congured
together as a single 16x1 dual-port RAM with one write
port and two read ports. Simultaneous read and write
operations to the same or different addresses are
supported.
RAM conguration options are selected by placing the
appropriate library symbol.
Choosing a RAM Conguration Mode
The appropriate choice of RAM mode for a given design
should be based on timing and resource requirements,
desired functionality, and the simplicity of the design pro-
cess. Recommended usage is shown in Table 4.
The difference between level-sensitive, edge-triggered,
and dual-port RAM is only in the write operation. Read
operation and timing is identical for all modes of operation.
RAM Inputs and Outputs
The F1-F4 and G1-G4 inputs to the function generators act
as address lines, selecting a particular memory cell in each
look-up table.
The functionality of the CLB control signals changes when
the function generators are congured as RAM. The
DIN/H2, H1, and SR/H0 lines become the two data inputs
(D0, D1) and the Write Enable (WE) input for the 16x2
memory. When the 32x1 conguration is selected, D1 acts
as the fth address bit and D0 is the data input.
The contents of the memory cell(s) being addressed are
available at the F’ and G’ function-generator outputs. They
can exit the CLB through its X and Y outputs, or can be cap-
tured in the CLB ip-op(s).
Conguring the CLB function generators as Read/Write
memory does not affect the functionality of the other por-
Table 3: Supported RAM Modes
16
x
1
16
x
2
32
x
1
Edge-
Triggered
Timing
Level-
Sensitive
Timing
Single-Port
√√√
√
Dual-Port
√
Table 4: RAM Mode Selection
Level-Sens
itive
Edge-Trigg
ered
Dual-Port
Edge-Trigg
ered
Use for New
Designs?
No
Yes
Size (16x1,
Registered)
1/2 CLB
1 CLB
Simultaneous
Read/Write
No
Yes
Relative
Performance
X2X
2X (4X
effective)
Product Obsolete or Under Obsolescence
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| XC4003E-3PG120C | 功能描述:IC FPGA C-TEMP 5V 3-SPD 120-CPGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
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| XC4003E-3PQ100C | 功能描述:IC FPGA 100 CLB'S 100-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
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