參數(shù)資料
型號： XC4005XL-09PQ160C
廠商： Xilinx Inc
文件頁數(shù)： 6/16頁
文件大?。?/td> 0K
描述： IC FPGA C-TEMP 3.3V 160-PQFP
產(chǎn)品變化通告： Product Discontinuation 27/Apr/2010
標準包裝： 1
系列： XC4000E/X
LAB/CLB數(shù)： 196
邏輯元件/單元數(shù)： 466
RAM 位總計： 6272
輸入/輸出數(shù)： 112
門數(shù)： 5000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-86
DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
XC4000XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values are expressed in nanoseconds unless otherwise noted.
-3
-2
-1
-09
-08
Description
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clocks
Clock High
Clock Low
TCH
TCL
3.0
2.8
2.5
2.3
2.1
Propagation Delays
Clock (OK) to Pad
Output (O) to Pad
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid
Output (O) to Pad via Fast Output MUX
Select (OK) to Pad via Fast MUX
TOKPOF
TOPF
TTSHZ
TTSONF
TOFPF
TOKFPF
5.0
4.1
4.0
4.4
5.5
5.1
4.3
3.6
3.5
3.8
4.8
4.5
3.8
3.1
3.0
3.3
4.2
3.9
3.5
3.0
2.9
3.3
4.0
3.7
3.3
2.8
2.9
3.3
3.7
3.4
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
TOOK
TOKO
TECOK
TOKEC
0.5
0.0
0.3
0.4
0.0
0.2
0.3
0.0
0.1
0.3
0.0
0.3
0.0
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Pad
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
TMRW
TRPO*
19.8
14.3
15.9
18.5
20.5
23.2
25.1
27.1
29.7
31.7
33.7
39.0
17.3
12.5
13.8
16.1
17.8
20.1
21.9
23.6
25.9
27.6
29.3
33.9
15.0
10.9
12.0
14.0
15.5
17.5
19.0
20.5
22.5
24.0
25.5
29.5
14.0
10.3
11.4
13.3
14.7
16.6
17.6
19.4
21.4
22.8
24.2
28.0
14.0
19.3
23.5
Slew Rate Adjustment
For output SLOW option add
TSLOW
3.0
2.5
2.0
1.7
1.6
Note: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads.
* Indicates Minimum Amount of Time to Assure Valid Data.
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