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參數(shù)資料
| 型號： | XC4005XL-09PQ208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA C-TEMP 3.3V 208-PQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 27/Apr/2010 |
| 標準包裝： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 196 |
| 邏輯元件/單元數(shù)： | 466 |
| RAM 位總計： | 6272 |
| 輸入/輸出數(shù)： | 112 |
| 門數(shù)： | 5000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-74
DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
D.C. Characteristics Over Recommended Operating Conditions
Power-0n Power Supply Requirements
Xilinx FPGAs require a minimum rated power supply current capacity to insure proper initialization, and the power supply
ramp-up time does affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. The
slowest ramp-up time is 50 ms. Current capacity is not specified for a ramp-up time faster than 2ms. The current capacity
varies linealy with ramp-up time, e.g., an XC4036XL with a ramp-up time of 25 ms would require a capacity predicted by the
point on the straight line drawn from 1A at 120
μs to 500 mA at 50 ms at the 25 ms time mark. This point is approximately
750 mA .
Symbol
Description
Min
Max
Units
VOH
High-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL)
2.4
V
High-level output voltage @ IOH = -500 μA, (LVCMOS)
90% VCC
V
VOL
Low-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL) (Note 1)
0.4
V
Low-level output voltage @ IOL = 1500 μA, (LVCMOS)
10% VCC
V
VDR
Data Retention Supply Voltage (below which configuration data may be lost)
2.5
V
ICCO
Quiescent FPGA supply current (Note 2)
5
mA
IL
Input or output leakage current
-10
+10
μA
CIN
Input capacitance (sample tested)
BGA, SBGA, PQ, HQ, MQ
packages
10
pF
PGA packages
16
pF
IRPU
Pad pull-up (when selected) @ Vin = 0 V (sample tested)
0.02
0.25
mA
IRPD
Pad pull-down (when selected) @ Vin = 3.6 V (sample tested)
0.02
0.15
mA
IRLL
Horizontal Longline pull-up (when selected) @ logic Low
0.3
2.0
mA
Note 1:
With up to 64 pins simultaneously sinking 12 mA.
Note 2:
With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating.
Product
Description
Ramp-up Time
Fast (120
μs)
Slow (50 ms)
XC4005 - 36XL
Minimum required current supply
1 A
500 mA
XC4044- 62XL
Minimum required current supply
2 A
500 mA
XC4085XL1
Minimum required current supply
2 A1
500 mA
Notes:
1. The XC4085XL fast ramp-up time is 5 ms.
Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may
result in a larger initialization current.
This specification applies to Commercial and Industrial grade products only.
Ramp-up Time is measured from 0 VDC to 3.6 VDC. Peak current required lasts less than 3 ms, and occurs near the
internal power on reset threshold voltage. After initialization and before configuration, ICCmax is less than 10 mA.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4005XL-09PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4005XL-09PQ208M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4005XL-09TQ144C | 功能描述:IC FPGA C-TEMP 3.3V 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4005XL-09TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4005XL-09TQ144M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
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