參數(shù)資料
型號： XC4005XL-09TQ144C
廠商： Xilinx Inc
文件頁數(shù)： 12/16頁
文件大?。?/td> 0K
描述： IC FPGA C-TEMP 3.3V 144-TQFP
產(chǎn)品變化通告： Product Discontinuation 27/Apr/2010
標(biāo)準(zhǔn)包裝： 1
系列： XC4000E/X
LAB/CLB數(shù)： 196
邏輯元件/單元數(shù)： 466
RAM 位總計： 6272
輸入/輸出數(shù)： 112
門數(shù)： 5000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
R
DS005 (v2.0) March 1, 2013 - Product Specification
6-77
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
XC4000XL CLB Characteristics
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
CLB Switching Characteristic Guidelines
Speed Grade
-3
-2
-1
-09
-08
Description
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
C inputs via DIN/H2 via H to X/Y outputs
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)
TILO
TIHO
TITO
THH0O
THH1O
THH2O
TCBYP
1.6
2.7
2.9
2.5
2.4
2.5
1.5
2.4
2.6
2.2
2.1
2.2
1.3
2.2
2.0
1.9
2.0
1.1
1.2
2.0
1.8
1.6
1.8
1.0
1.1
1.9
1.8
1.5
1.8
0.9
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to COUT
CIN through function generators to X/Y outputs
CIN to COUT, bypass function generators
Carry Net Delay, COUT to CIN
TOPCY
TASCY
TINCY
TSUM
TBYP
TNET
2.7
3.3
2.0
2.8
0.26
0.32
2.3
2.9
1.8
2.6
0.23
0.28
2.0
2.5
1.5
2.4
0.20
0.25
1.6
1.8
1.0
1.7
0.14
0.24
1.6
1.8
0.9
1.5
0.14
0.24
Sequential Delays
Clock K to Flip-Flop outputs Q
Clock K to Latch outputs Q
TCKO
TCKLO
2.1
1.9
1.6
1.5
1.4
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
CIN input via F/G and H
TICK
TIHCK
THH0CK
THH1CK
THH2CK
TDICK
TECCK
TRCK
TCCK
TCHCK
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
1.0
1.9
1.7
1.6
1.7
0.8
0.9
0.5
2.1
3.0
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
0.8
1.6
1.4
1.2
1.4
0.6
0.7
0.4
1.3
2.1
0.8
1.5
1.4
1.1
1.4
0.6
0.7
0.4
1.2
2.0
Hold Time after Clock K
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via DIN/H2 through H
C inputs via DIN/H2
C inputs via EC
C inputs via SR, going Low (inactive)
TCKI
TCKIH
TCKHH0
TCKHH1
TCKHH2
TCKDI
TCKEC
TCKR
0
Clock
Clock High time
Clock Low time
TCH
TCL
3.0
2.8
2.5
2.3
2.1
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
TRPW
TRIO
3.0
3.7
2.8
3.2
2.5
2.8
2.3
2.7
2.3
2.6
Global Set/Reset
Minimum GSR Pulse Width
TMRW
19.8
17.3
15.0
14.0
Delay from GSR input to any Q
TMRQ
See Table on page 85 for TRRI values per device.
Toggle Frequency (MHz) (for export control)
FTOG (MHz)
166
179
200
217
238
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