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參數(shù)資料
| 型號(hào)： | XC4006E-4TQ144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 29/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA I-TEMP 5V 4SPD 144-TQFP |
| 產(chǎn)品變化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 256 |
| 邏輯元件/單元數(shù)： | 608 |
| RAM 位總計(jì)： | 8192 |
| 輸入/輸出數(shù)： | 113 |
| 門數(shù)： | 6000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
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R
May 14, 1999 (Version 1.6)
6-39
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
The top and bottom Global Early buffers are about 1 ns
slower clock to out than the left and right Global Early buff-
ers.
The Global Early buffers can be driven by either semi-ded-
icated pads or internal logic. They share pads with the Glo-
bal Low-Skew buffers, so a single net can drive both global
buffers, as described above.
To use a Global Early buffer, place a BUFGE element in a
schematic or in HDL code. If desired, attach a LOC
attribute or property to direct placement to the designated
location. For example, attach a LOC=T attribute or property
to direct that a BUFGE be placed in one of the two Global
Early buffers on the top edge of the device, or a LOC=TR to
indicate the Global Early buffer on the top edge of the
device, on the right.
Power Distribution
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vcc and Ground ring sur-
rounding the logic array provides power to the I/O drivers,
as shown in Figure 39. An independent matrix of Vcc and
Ground lines supplies the interior logic of the device.
This power distribution grid provides a stable supply and
ground for all internal logic, providing the external package
power pins are all connected and appropriately de-coupled.
Typically, a 0.1
F capacitor connected between each Vcc
pin and the board’s Ground plane will provide adequate
de-coupling.
Output buffers capable of driving/sinking the specied 12
mA loads under specied worst-case conditions may be
capable of driving/sinking up to 10 times as much current
under best case conditions.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be benecial to locate heavily
loaded output buffers near the Ground pads. The I/O Block
output buffers have a slew-rate limited mode (default) which
should be used where output rise and fall times are not
speed-critical.
Pin Descriptions
There are three types of pins in the XC4000 Series
devices:
Permanently dedicated pins
User I/O pins that can have special functions
Unrestricted user-programmable I/O pins.
Before and during conguration, all outputs not used for the
conguration process are 3-stated with a 50 k
- 100 k
pull-up resistor.
After conguration, if an IOB is unused it is congured as
an input with a 50 k
- 100 k pull-up resistor.
XC4000 Series devices have no dedicated Reset input.
Any user I/O can be congured to drive the Global
Set/Reset net, GSR.
See “Global Set/Reset” on page 11
for more information on GSR.
XC4000 Series devices have no Powerdown control input,
as
the
XC3000
and
XC2000
families
do.
The
XC3000/XC2000 Powerdown control also 3-stated all of the
device
I/O pins. For XC4000 Series devices, use the global 3-state
net, GTS, instead. This net 3-states all outputs, but does
not place the device in low-power mode. See “IOB Output
Signals” on page 23 for more information on GTS.
Device pins for XC4000 Series devices are described in
Table 16. Pin functions during conguration for each of the
seven conguration modes are summarized in Table 22 on
page 58, in the “Conguration Timing” section.
GND
Ground and
Vcc Ring for
I/O Drivers
Vcc
GND
Vcc
Logic
Power Grid
X5422
Figure 39: XC4000 Series Power Distribution
Product Obsolete or Under Obsolescence
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