- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4166 > XC4008E-2PG191C (Xilinx Inc)IC FPGA C-TEMP 5V 2SPD 191-CPGA PDF資料下載
參數(shù)資料
| 型號： | XC4008E-2PG191C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 36/68頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA C-TEMP 5V 2SPD 191-CPGA |
| 產(chǎn)品變化通告： | XC4000(E,L) Discontinuation 01/April/2002 |
| 標準包裝： | 12 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 324 |
| 邏輯元件/單元數(shù)： | 770 |
| RAM 位總計： | 10368 |
| 輸入/輸出數(shù)： | 144 |
| 門數(shù)： | 8000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 191-BCBGA |
| 供應(yīng)商設(shè)備封裝： | 191-CPGA（47.25x47.25） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
R
May 14, 1999 (Version 1.6)
6-45
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Table 17: Boundary Scan Instructions
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant dur-
ing conguration. In some applications, a situation may
occur where TMS or TCK is driven during conguration.
This may cause the device to go into boundary scan mode
and disrupt the conguration process.
To prevent activation of boundary scan during congura-
tion, do either of the following:
TMS: Tie High to put the Test Access Port controller
in a benign RESET state
TCK: Tie High or Low—don't toggle this clock input.
For more information regarding boundary scan, refer to the
Xilinx Application Note XAPP 017.001, “
Boundary Scan in
XC4000E Devices.“
Conguration
Conguration is the process of loading design-specic pro-
gramming data into one or more FPGAs to dene the func-
tional
operation
of
the
internal
blocks
and
their
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip. XC4000
Series devices use several hundred bits of conguration
data per CLB and its associated interconnects. Each con-
guration bit denes the state of a static memory cell that
controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The XACT
step
development system translates the design into a netlist le.
It automatically partitions, places and routes the logic and
generates the conguration data in PROM format.
Special Purpose Pins
Three conguration mode pins (M2, M1, M0) are sampled
prior to conguration to determine the conguration mode.
After conguration, these pins can be used as auxiliary
connections. M2 and M0 can be used as inputs, and M1
can be used as an output. The XACT
step development sys-
tem does not use these resources unless they are explicitly
specied in the design entry. This is done by placing a spe-
cial pad symbol called MD2, MD1, or MD0 instead of the
input or output pad symbol.
In XC4000 Series devices, the mode pins have weak
pull-up resistors during conguration. With all three mode
pins High, Slave Serial mode is selected, which is the most
popular conguration mode. Therefore, for the most com-
mon conguration mode, the mode pins can be left uncon-
nected. (Note, however, that the internal pull-up resistor
value can be as high as 100 k
.) After conguration, these
pins can individually have weak pull-up or pull-down resis-
tors, as specied in the design. A pull-down resistor value
of 4.7 k
is recommended.
These pins are located in the lower left chip corner and are
near the readback nets. This location allows convenient
routing if compatibility with the XC2000 and XC3000 family
conventions of M0/RT, M1/RD is desired.
Instruction I2
I1
I0
Test
Selected
TDO Source
I/O Data
Source
0
EXTEST
DR
0
1
SAMPLE/PR
ELOAD
DR
Pin/Logic
0
1
0
USER 1
BSCAN.
TDO1
User Logic
0
1
USER 2
BSCAN.
TDO2
User Logic
1
0
READBACK
Readback
Data
Pin/Logic
1
0
1
CONFIGURE
DOUT
Disabled
1
0
Reserved
—
1
BYPASS
Bypass
Register
—
Bit 0 ( TDO end)
Bit 1
Bit 2
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MD1.T
MD1.O
MD1.I
MD0.I
MD2.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
B SCANT.UPD
(TDI end)
X6075
Figure 42:
Boundary Scan Bit Sequence
TDI
TMS
TCK
TDO1
TDO2
TDO
DRCK
IDLE
SEL1
SEL2
TDI
TMS
TCK
TDO
BSCAN
To User
Logic
IBUF
Optional
From
User Logic
To User
Logic
X2675
Figure 43: Boundary Scan Schematic Example
Product Obsolete or Under Obsolescence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC4008E-2PC84I | IC FPGA I-TEMP 5V 2SPD 84-PLCC |
| XC4008E-2PC84C | IC FPGA C-TEMP 5V 2SPD 84-PLCC |
| XC4008E-1PQ208C | IC FPGA C-TEMP 5V 1SPD 208-PQFP |
| XC4008E-1PQ160C | IC FPGA C-TEMP 5V 1SPD 160-PQFP |
| IDT71V3559S85BQG8 | IC SRAM 4MBIT 85NS 165FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4008E-2PG191I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC4008E-2PG191M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC4008E-2PQ160C | 功能描述:IC FPGA C-TEMP 5V 2SPD 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4008E-2PQ160I | 功能描述:IC FPGA I-TEMP 5V 2SPD 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4008E-2PQ208C | 功能描述:IC FPGA C-TEMP 5V 2SPD 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
發(fā)布緊急采購，3分鐘左右您將得到回復。