參數(shù)資料
型號(hào)： XC4010XL-1TQ144I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 52/68頁(yè)
文件大?。?/td> 0K
描述： IC FPGA I-TEMP 3.3V 1SPD 144TQFP
產(chǎn)品變化通告： Product Discontinuation 27/Apr/2010
標(biāo)準(zhǔn)包裝： 1
系列： XC4000E/X
LAB/CLB數(shù)： 400
邏輯元件/單元數(shù)： 950
RAM 位總計(jì)： 12800
輸入/輸出數(shù)： 113
門數(shù)： 10000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-60
May 14, 1999 (Version 1.6)
Conguration Timing
The seven conguration modes are discussed in detail in
this section. Timing specications are included.
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial conguration bitstream must
be available at the DIN input of the lead FPGA a short
setup time before each rising CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overows the lead device—on its DOUT pin.
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the sub-
sequent rising CCLK edge.
Figure 51 shows a full master/slave system. An XC4000
Series device in Slave Serial mode should be connected as
shown in the third device from the left.
Slave Serial mode is selected by a <111> on the mode pins
(M2, M1, M0). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resis-
tors during conguration.
Figure 52: Slave Serial Mode Programming Switching Characteristics
XC4000E/X
MASTER
SERIAL
XC4000E/X,
XC5200
SLAVE
XC3100A
SLAVE
XC1700D
PROGRAM
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
NOTE:
M2, M1, M0 can be shorted
to VCC if not used as I/O
M2
M0 M1
DOUT
CCLK
CLK
VCC
+5 V
DATA
CE
CEO
VPP
RESET/OE
DONE
DIN
LDC
INIT
DONE
PROGRAM
D/P
INIT
RESET
CCLK
DIN
CCLK
DIN
DOUT
M2
M0 M1
M1
PWRDN
M0
M2
(Low Reset Option Used)
4.7 K
4.7 K
4.7 K
4.7 K
4.7 K
4.7 K
4.7 K
VCC
X9025
N/C
Figure 51: Master/Slave Serial Mode Circuit Diagram
4 TCCH
Bit n
Bit n + 1
Bit n
Bit n - 1
3 TCCO
5 TCCL
2 TCCD
1 TDCC
DIN
CCLK
DOUT
(Output)
X5379
Description
Symbol
Min
Max
Units
CCLK
DIN setup
1
TDCC
20
ns
DIN hold
2
TCCD
0ns
DIN to DOUT
3
TCCO
30
ns
High time
4
TCCH
45
ns
Low time
5
TCCL
45
ns
Frequency
FCC
10
MHz
Note: Conguration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Product Obsolete or Under Obsolescence
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XC4010XL-1TQ144M 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
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XC4010XL-1TQ176I 功能描述:IC FPGA I-TEMP 3.3V 1SPD 176TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XC4010XL-1TQ176M 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4010XL-2BG256C 功能描述:IC FPGA C-TEMP 3.3V 2SPD 256PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
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