- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4159 > XC4010XL-3TQ144I (Xilinx Inc)IC FPGA I-TEMP 3.3V 3SPD 144TQFP PDF資料下載
參數(shù)資料
| 型號： | XC4010XL-3TQ144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 13/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA I-TEMP 3.3V 3SPD 144TQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 27/Apr/2010 |
| 標準包裝： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 400 |
| 邏輯元件/單元數(shù)： | 950 |
| RAM 位總計： | 12800 |
| 輸入/輸出數(shù)： | 113 |
| 門數(shù)： | 10000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-24
May 14, 1999 (Version 1.6)
Any XC4000 Series 5-Volt device with its outputs cong-
ured in TTL mode can drive the inputs of any typical
3.3-Volt device. (For a detailed discussion of how to inter-
face between 5 V and 3.3 V devices, see the 3V Products
section of
The Programmable Logic Data Book.)
Supported destinations for XC4000 Series device outputs
are shown in Table 12.
An output can be congured as open-drain (open-collector)
by placing an OBUFT symbol in a schematic or HDL code,
then tying the 3-state pin (T) to the output signal, and the
input pin (I) to Ground. (See Figure 18.)
Table 12: Supported Destinations for XC4000 Series
Outputs
Output Slew Rate
The slew rate of each output buffer is, by default, reduced,
to minimize power bus transients when switching non-criti-
cal signals. For critical signals, attach a FAST attribute or
property to the output buffer or ip-op.
For XC4000E devices, maximum total capacitive load for
simultaneous fast mode switching in the same direction is
200 pF for all package pins between each Power/Ground
pin
pair.
For
XC4000X
devices,
additional
internal
Power/Ground pin pairs are connected to special Power
and Ground planes within the packages, to reduce ground
bounce. Therefore, the maximum total capacitive load is
300 pF between each external Power/Ground pin pair.
Maximum loading may vary for the low-voltage devices.
For slew-rate limited outputs this total is two times larger for
each device type: 400 pF for XC4000E devices and 600 pF
for XC4000X devices. This maximum capacitive load
should not be exceeded, as it can result in ground bounce
of greater than 1.5 V amplitude and more than 5 ns dura-
tion. This level of ground bounce may cause undesired
transient behavior on an output, or in the internal logic. This
restriction is common to all high-speed digital ICs, and is
not particular to Xilinx or the XC4000 Series.
XC4000 Series devices have a feature called “Soft
Start-up,” designed to reduce ground bounce when all out-
puts are turned on simultaneously at the end of congura-
tion.
When the conguration process is nished and the
device starts up, the rst activation of the outputs is auto-
matically slew-rate limited. Immediately following the initial
activation of the I/O, the slew rate of the individual outputs
is determined by the individual conguration option for each
IOB.
Global Three-State
A separate Global 3-State line (not shown in Figure 15 or
Figure 16) forces all FPGA outputs to the high-impedance
state, unless boundary scan is enabled and is executing an
EXTEST instruction. This global net (GTS) does not com-
pete with other routing resources; it uses a dedicated distri-
bution network.
GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. A specic pin loca-
tion can be assigned to this input using a LOC attribute or
property, just as with any other user-programmable pad. An
inverter can optionally be inserted after the input buffer to
invert the sense of the Global 3-State signal. Using GTS is
similar to GSR. See Figure 2 on page 11 for details.
Alternatively, GTS can be driven from any internal node.
Destination
XC4000 Series
Outputs
3.3 V,
CMOS
5 V,
TTL
5 V,
CMOS
Any typical device, Vcc = 3.3 V,
CMOS-threshold inputs
√√
some1
1. Only if destination device has 5-V tolerant inputs
Any device, Vcc = 5 V,
TTL-threshold inputs
√√√
Any device, Vcc = 5 V,
CMOS-threshold inputs
Unreliable
Data
√
X6702
OPAD
OBUFT
Figure 18: Open-Drain Output
Product Obsolete or Under Obsolescence
相關PDF資料 |
PDF描述 |
|---|---|
| XC4010XL-3TQ144C | IC FPGA C-TEMP 3.3V 3SPD 144TQFP |
| AMC44DREH-S734 | CONN EDGECARD 88POS .100 EYELET |
| 487223-1 | 010 HOUSING FFC RCPT 100CL DR |
| 88859-4 | 012 HOUSING FFC RCPT SR 100CL |
| 88859-7 | 014 HOUSING FFC RCPT SR 100CL |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4010XL-3TQ144M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4010XL-3TQ176C | 功能描述:IC FPGA C-TEMP 3.3V 3SPD 176TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4010XL-3TQ176C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
| XC4010XL-3TQ176I | 功能描述:IC FPGA I-TEMP 3.3V 3SPD 176TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4010XL-3TQ176M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復。