參數(shù)資料
型號(hào)： XC4013E-2BG225I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 4/68頁(yè)
文件大?。?/td> 0K
描述： IC FPGA I-TEMP 5V 2SPD 225-PBGA
產(chǎn)品變化通告： Product Discontinuation 28/Jul/2010
標(biāo)準(zhǔn)包裝： 1
系列： XC4000E/X
LAB/CLB數(shù)： 576
邏輯元件/單元數(shù)： 1368
RAM 位總計(jì)： 18432
輸入/輸出數(shù)： 192
門數(shù)： 13000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 225-BBGA
供應(yīng)商設(shè)備封裝： 225-PBGA
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-16
May 14, 1999 (Version 1.6)
Figure 8 shows the write timing for level-sensitive, sin-
gle-port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port level-sensitive mode are shown in
Figure 9 and Figure 10 show block diagrams of a CLB con-
gured as 16x2 and 32x1 level-sensitive, single-port RAM.
Initializing RAM at Conguration
Both RAM and ROM implementations of the XC4000
Series devices are initialized during conguration. The ini-
tial contents are dened via an INIT attribute or property
attached to the RAM or ROM symbol, as described in the
schematic library guide. If not dened, all RAM contents
are initialized to all zeros, by default.
RAM initialization occurs only during conguration. The
RAM content is not affected by Global Set/Reset.
Table 7: Single-Port Level-Sensitive RAM Signals
G'
G1 G4
F1 F4
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6748
4
MUX
F'
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
READ
ADDRESS
READ
ADDRESS
WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK)
WRITE PULSE
MUX
4
C1 C4
4
WE
D1
D0
EC
Figure 7: 16x1 Edge-Triggered Dual-Port RAM
RAM Signal
CLB Pin
Function
D
D0 or D1
Data In
A[3:0]
F1-F4 or G1-G4
Address
WE
Write Enable
O
F’ or G’
Data Out
WC
T
ADDRESS
WRITE ENABLE
DATA IN
AS
T
WP
T
DS
T
DH
T
REQUIRED
AH
T
X6462
Figure 8: Level-Sensitive RAM Write Timing
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
XC4013E-2BG225C IC FPGA C-TEMP 5V 2SPD 225-PBGA
485897-2 CONN PLUG 4POS HOUSING W/DETENT
1-487769-3 015 HOUSING FFC RCPT 100CL SR
IDT71V546XS100PFG IC SRAM 4MBIT 100MHZ 100TQFP
487769-4 CONN RECEPT 6 POS .100 SLIMLINE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4013E-2BG240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-2BG240I 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-2BG240M 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-2CB240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-2CB240I 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*