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參數(shù)資料
| 型號： | XC4013E-2CB240M |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| 中文描述： | XC4000E和XC4000X系列現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大小： | 21K |
| 代理商： | XC4013E-2CB240M |
4
XC4000E Logic Cell Array Family
ADVANCE
INFORMATION
Speed Grade
-4
-3
-2
Description
Symbol
Min
Max
Min Max
Min Max Units
Combinatorial Delays
F/G inputs to X/Y outputs
T
ILO
2.0
ns
F/G inputs via H’ to X/Y outputs
T
IHO
3.6
ns
C inputs via H’ to X/Y outputs
T
HHO
2.9
ns
CLB Fast Carry Logic
Operand inputs (F1,F2,G1,G4) to COUT
T
OPCY
2.6
ns
Add/Subtract input (F3) to COUT
T
ASCY
4.4
ns
Initialization inputs (F1,F3) to COUT
T
INCY
1.7
ns
C
IN through function generators to X/Y outputs
T
SUM
3.3
ns
C
IN to COUT, bypass function generators.
T
BYP
0.7
ns
Sequential Delays
Clock K to outputs Q
T
CKO
2.4
ns
Set-up Time before Clock K
F/G inputs
T
ICK
2.3
ns
F/G inputs via H’
T
IHCK
4.0
ns
C inputs via H1
T
HHCK
3.3
ns
C inputs via DIN
T
DICK
1.9
ns
C inputs via EC
T
ECCK
2.6
ns
C inputs via S/R, going Low (inactive)
T
RCK
1.7
ns
C
IN
input via F'/G'
T
CCK
ns
C
IN
input via F'/G' and H'
T
CHCK
ns
Hold Time after Clock K
F/G inputs
T
CKI
0ns
F/G inputs via H’
T
CKIH
0ns
C inputs via H1
T
CKHH
0ns
C inputs via DIN
T
CKDI
0ns
C inputs via EC
T
CKEC
0ns
C inputs via S/R, going Low (inactive)
T
CKR
0ns
Clock
Clock High time
T
CH
4.0
ns
Clock Low time
T
CL
4.0
ns
Set/Reset Direct
Width (High)
T
RPW
4.0
ns
Delay from C inputs via S/R, going High to Q
T
RIO
4.0
ns
Master Set/Reset*
Width (High or Low)
T
MRW
18.9
ns
Delay from Global Set/Reset net to Q
T
MRQ
14.4
ns
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
*
Timing is based on the XC4005E. For other devices see XACT timing calculator.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC4013E-4TQ240C | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-4TQ240I | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-4TQ240M | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-4VQ240C | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-4VQ240I | XC4000E and XC4000X Series Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4013E-2HG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2HG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2HG240M | 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2HQ208C | 功能描述:IC FPGA C-TEMP 5V 2SPD 208-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4013E-2HQ208I | 功能描述:IC FPGA I-TEMP 5V 2SPD 208-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
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