參數(shù)資料
型號： XC4013E-4PQ240C
廠商： Xilinx Inc
文件頁數(shù)： 40/68頁
文件大小： 0K
描述： IC FPGA C-TEMP 5V 4SPD 240-PQFP
產品變化通告： Product Discontinuation 28/Jul/2010
標準包裝： 24
系列： XC4000E/X
LAB/CLB數(shù)： 576
邏輯元件/單元數(shù)： 1368
RAM 位總計： 18432
輸入/輸出數(shù)： 192
門數(shù)： 13000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 240-BFQFP
供應商設備封裝： 240-PQFP（32x32）
R
May 14, 1999 (Version 1.6)
6-49
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Notes:
1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading ones at the beginning of the header.
Cyclic Redundancy Check (CRC) for
Conguration and Readback
The Cyclic Redundancy Check is a method of error detec-
tion in data transmission applications. Generally, the trans-
mitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and com-
pares the result with the received checksum.
Each data frame of the conguration bitstream has four
error bits at the end, as shown in Table 19. If a frame data
error is detected during the loading of the FPGA, the con-
guration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in Figure 45. The checksum consists of the 11 most signif-
icant bits of the 16-bit code. A change in the checksum indi-
cates a change in the Readback bitstream. A comparison
to a previous checksum is meaningful only if the readback
data is independent of the current device state. CLB out-
puts should not be included (Read Capture option not
Table 20: XC4000E Program Data
Device
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
Max Logic Gates
3,000
5,000
6,000
8,000
10,000
13,000
20,000
25,000
CLBs
(Row x Col.)
100
(10 x 10)
196
(14 x 14)
256
(16 x 16)
324
(18 x 18)
400
(20 x 20)
576
(24 x 24)
784
(28 x 28)
1,024
(32 x 32)
IOBs
80
112
128
144
160
192
224
256
Flip-Flops
360
616
768
936
1,120
1,536
2,016
2,560
Bits per Frame
126
166
186
206
226
266
306
346
Frames
428
572
644
716
788
932
1,076
1,220
Program Data
53,936
94,960
119,792
147,504
178,096
247,920
329,264
422,128
PROM Size
(bits)
53,984
95,008
119,840
147,552
178,144
247,968
329,312
422,176
Table 21: XC4000EX/XL Program Data
Device
XC4002XL XC4005
XC4010
XC4013
XC4020
XC4028
XC4036
XC4044
XC4052
XC4062
XC4085
Max Logic
Gates
2,000
5,000
10,000
13,000
20,000
28,000
36,000
44,000
52,000
62,000
85,000
CLBs
(Row x
Column)
64
(8 x 8)
196
(14 x 14)
400
(20 x 20)
576
(24 x 24)
784
(28 x 28)
1,024
(32 x 32)
1,296
(36 x 36)
1,600
(40 x 40)
1,936
(44 x 44)
2,304
(48 x 48)
3,136
(56 x 56)
IOBs
64
112
160
192
224
256
288
320
352
384
448
Flip-Flops
256
616
1,120
1,536
2,016
2,560
3,168
3,840
4,576
5,376
7,168
Bits per
Frame
133
205
277
325
373
421
469
517
565
613
709
Frames
459
741
1,023
1,211
1,399
1,587
1,775
1,963
2,151
2,339
2,715
Program Data
61,052
151,910
283,376
393,580
521,832
668,124
832,480
1,014,876 1,215,320 1,433,804 1,924,940
PROM Size
(bits)
61,104
151,960
283,424
393,632
521,880
668,172
832,528
1,014,924 1,215,368 1,433,852 1,924,992
Notes:
1. Bits per frame = (13 x number of rows) + 9 for the top + 17 for the bottom + 8 + 1 start bit + 4 error check bits.
Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4.
Program data = (bits per frame x number of frames) + 5 postamble bits.
PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte.
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end
of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading “ones” at the beginning of the header.
Product Obsolete or Under Obsolescence
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相關代理商/技術參數(shù)
參數(shù)描述
XC4013E-4PQ240C0167 制造商:Xilinx 功能描述:
XC4013E-4PQ240C0377 制造商:Xilinx 功能描述:
XC4013E-4PQ240I 功能描述:IC FPGA I-TEMP 5V 4SPD 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XC4013E-4PQ240M 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-4TQ240C 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
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