參數(shù)資料
型號(hào): XC4013XL-1BG256C
廠商: Xilinx Inc
文件頁數(shù): 3/16頁
文件大?。?/td> 0K
描述: IC FPGA C-TEMP 3.3V 1SPD 256PBGA
產(chǎn)品變化通告: Product Discontinuation 27/Apr/2010
標(biāo)準(zhǔn)包裝: 1
系列: XC4000E/X
LAB/CLB數(shù): 576
邏輯元件/單元數(shù): 1368
RAM 位總計(jì): 18432
輸入/輸出數(shù): 192
門數(shù): 13000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-BBGA
供應(yīng)商設(shè)備封裝: 256-PBGA
R
DS005 (v2.0) March 1, 2013 - Product Specification
6-83
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
Global Early Clock BUFGEs 1, 2, 5, and 6 Set-up and Hold for IFF and FCL
Speed Grade
-3
-2
-1
-09
-08
Units
Description
Symbol
Device
Min
Input Setup and Hold
Times
No Delay
Global Early Clock and IFF
Global Early Clock and
FCL
TPSEN/TPHEN
TPFSEN/TPFHEN
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
2.8 / 1.5
1.2 / 4.1
1.2 / 4.4
1.2 / 4.7
1.2 / 4.6
1.2 / 5.3
1.2 / 6.7
1.2 / 6.5
1.2 / 6.7
1.2 / 8.4
1.2 / 8.7
2.5 / 1.3
1.1 / 3.6
1.1 / 3.8
1.1 / 4.1
1.1 / 4.0
1.1 / 4.6
1.1 / 5.8
1.1 / 5.7
1.1 / 5.8
1.1 / 7.3
1.1 / 7.5
2.2 / 1.2
0.9 / 3.1
0.9 / 3.3
0.9 / 3.6
0.9 / 3.5
0.9 / 4.0
0.9 / 5.1
0.9 / 4.9
0.9 / 5.1
0.9 / 6.3
0.9 / 6.6
1.9 / 1.0
0.8 / 2.7
0.8 / 2.9
0.8 / 3.1
0.8 / 3.0
0.8 / 3.5
0.8 / 4.4
0.8 / 4.3
0.8 / 4.4
0.8 / 5.5
0.8 / 5.7
0.5 / 2.7
0.5 / 3.7
0.5 / 4.7
ns
Partial Delay
Global Early Clock and IFF
Global Early Clock and
FCL
TPSEP/TPHEP
TPFSEP/TPFHEP
XC4002XL
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
8.1 / 0.9
9.0 / 0.0
11.9 / 0.0
6.4 / 0.0
10.8 / 0.0
14.0 / 0.0
7.0 / 0.0
14.6 / 0.0
16.4 / 0.0
9.0 / 0.8
16.7 / 0.0
7.0 / 0.8
8.5 / 0.0
10.4 / 0.0
5.9 / 0.0
10.3 / 0.0
12.2 / 0.0
6.6 / 0.0
12.7 / 0.0
14.3 / 0.0
8.6 / 0.8
14.5 / 0.0
6.1 / 0.7
8.0 / 0.0
9.0 / 0.0
5.4 / 0.0
9.8 / 0.0
10.6 / 0.0
6.2 / 0.0
11.0 / 0.0
12.4 / 0.0
8.2 / 0.8
12.6 / 0.0
5.3 / 0.6
7.5 / 0.0
8.0 / 0.0
4.9 / 0.0
9.0 / 0.0
9.8 / 0.0
5.2 / 0.0
10.8 / 0.0
11.4 / 0.0
7.0 / 0.8
11.6 / 0.0
4.4 / 0.0
4.7 / 0.0
6.3 / 0.5
ns
Full Delay
Global Early Clock and IFF TPSED/TPHED
XC4002XL
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
6.7 / 0.0
10.8 / 0.0
10.3 / 0.0
10.0 / 0.0
12.0 / 0.0
12.6 / 0.0
12.2 / 0.0
13.8 / 0.0
14.1 / 0.0
13.1 / 0.0
17.9 / 0.0
5.8 / 0.0
9.4 / 0.0
9.0 / 0.0
8.7 / 0.0
10.4 / 0.0
11.0 / 0.0
10.6 / 0.0
12.0 / 0.0
12.3 / 0.0
11.4 / 0.0
15.6 / 0.0
5.1 / 0.0
8.2 / 0.0
7.8 / 0.0
7.6 / 0.0
9.1 / 0.0
9.5 / 0.0
9.2 / 0.0
10.5 / 0.0
10.7 / 0.0
9.9 / 0.0
13.6 / 0.0
4.4 / 0.0
7.1 / 0.0
6.8 / 0.0
6.6 / 0.0
7.9 / 0.0
8.3 / 0.0
8.0 / 0.0
9.1 / 0.0
9.3 / 0.0
8.6 / 0.0
11.8 / 0.0
6.0 / 0.0
7.2 / 0.0
7.8 / 0.0
ns
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
Notes:
Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
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