參數(shù)資料
型號(hào): XC4013XL-1BG256I
廠商: Xilinx Inc
文件頁數(shù): 13/16頁
文件大?。?/td> 0K
描述: IC FPGA I-TEMP 3.3V 1SPD 256PBGA
產(chǎn)品變化通告: Product Discontinuation 27/Apr/2010
標(biāo)準(zhǔn)包裝: 1
系列: XC4000E/X
LAB/CLB數(shù): 576
邏輯元件/單元數(shù): 1368
RAM 位總計(jì): 18432
輸入/輸出數(shù): 192
門數(shù): 13000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-BBGA
供應(yīng)商設(shè)備封裝: 256-PBGA
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-78
DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
CLB Single-Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Single Port RAM
Speed Grade
-3
-2
-1
-09
-08
Size
Symbol Min
Max
Min
Max
Min
Max
Min Max Min Max
Write Operation
Address write cycle time (clock K period)
16x2
32x1
TWCS
TWCTS
9.0
8.4
7.7
7.4
Clock K pulse width (active edge)
16x2
32x1
TWPS
TWPTS
4.5
4.2
3.9
3.7
Address setup time before clock K
16x2
32x1
TASS
TASTS
2.2
2.0
1.7
1.6
1.7
Address hold time after clock K
16x2
32x1
TAHS
TAHTS
0
DIN setup time before clock K
16x2
32x1
TDSS
TDSTS
2.0
2.5
1.9
2.3
1.7
2.1
1.7
2.1
1.7
2.1
DIN hold time after clock K
16x2
32x1
TDHS
TDHTS
0
WE setup time before clock K
16x2
32x1
TWSS
TWSTS
2.0
1.8
1.7
1.6
1.5
1.6
1.5
1.6
1.5
WE hold time after clock K
16x2
32x1
TWHS
TWHTS
0
Data valid after clock K
16x2
32x1
TWOS
TWOTS
6.8
8.1
6.3
7.5
5.8
6.9
5.8
6.7
5.7
6.7
Read Operation
Address read cycle time
16x2
32x1
TRC
TRCT
4.5
6.5
3.1
5.5
2.6
3.8
2.6
3.8
2.6
3.8
Data Valid after address change (no
Write Enable)
16x2
32x1
TILO
TIHO
1.6
2.7
1.5
2.4
1.3
2.2
1.2
2.0
1.1
1.9
Address setup time before clock K
16x2
32x1
TICK
TIHCK
1.1
2.2
1.0
1.9
0.9
1.7
0.8
1.6
0.8
1.5
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XC4013XL-1HT144M 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4013XL-1HT176C 功能描述:IC FPGA C 3.3V 1SPD 176HTQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱:122-1789