• 參數(shù)資料
    型號(hào)： XC4013XL-3BG256C
    廠商： Xilinx Inc
    文件頁(yè)數(shù)： 67/68頁(yè)
    文件大?。?/td> 0K
    描述： IC FPGA C-TEMP 3.3V 3SPD 256PBGA
    產(chǎn)品變化通告： Product Discontinuation 27/Apr/2010
    標(biāo)準(zhǔn)包裝： 1
    系列： XC4000E/X
    LAB/CLB數(shù)： 576
    邏輯元件/單元數(shù)： 1368
    RAM 位總計(jì)： 18432
    輸入/輸出數(shù)： 192
    門(mén)數(shù)： 13000
    電源電壓： 3 V ~ 3.6 V
    安裝類(lèi)型： 表面貼裝
    工作溫度： 0°C ~ 85°C
    封裝/外殼： 256-BBGA
    供應(yīng)商設(shè)備封裝： 256-PBGA
    R
    XC4000E and XC4000X Series Field Programmable Gate Arrays
    6-12
    May 14, 1999 (Version 1.6)
    Supported CLB memory congurations and timing modes
    for single- and dual-port modes are shown in Table 3.
    XC4000 Series devices are the rst programmable logic
    devices with edge-triggered (synchronous) and dual-port
    RAM accessible to the user.
    Edge-triggered RAM simpli-
    es system timing. Dual-port RAM doubles the effective
    throughput of FIFO applications. These features can be
    individually programmed in any XC4000 Series CLB.
    Advantages of On-Chip and Edge-Triggered RAM
    The on-chip RAM is extremely fast. The read access time is
    the same as the logic delay.
    The write access time is
    slightly slower.
    Both access times are much faster than
    any off-chip solution, because they avoid I/O delays.
    Edge-triggered RAM, also called synchronous RAM, is a
    feature never before available in a Field Programmable
    Gate Array. The simplicity of designing with edge-triggered
    RAM, and the markedly higher achievable performance,
    add up to a signicant improvement over existing devices
    with on-chip RAM.
    Three application notes are available from Xilinx that dis-
    cuss edge-triggered RAM: “
    XC4000E Edge-Triggered and
    Dual-Port
    RAM
    Capability,”“Implementing
    FIFOs
    in
    XC4000E RAM,” and “Synchronous and Asynchronous
    FIFO Designs.” All three application notes apply to both
    XC4000E and XC4000X RAM.
    RAM Conguration Options
    The function generators in any CLB can be congured as
    RAM arrays in the following sizes:
    Two 16x1 RAMs: two data inputs and two data outputs
    with identical or, if preferred, different addressing for
    each RAM
    One 32x1 RAM: one data input and one data output.
    One F or G function generator can be congured as a 16x1
    RAM while the other function generators are used to imple-
    ment any function of up to 5 inputs.
    Additionally, the XC4000 Series RAM may have either of
    two timing modes:
    Edge-Triggered (Synchronous): data written by the
    designated edge of the CLB clock. WE acts as a true
    clock enable.
    Level-Sensitive (Asynchronous): an external WE signal
    acts as the write strobe.
    The selected timing mode applies to both function genera-
    tors within a CLB when both are congured as RAM.
    The number of read ports is also programmable:
    Single Port: each function generator has a common
    read and write port
    Dual Port: both function generators are congured
    together as a single 16x1 dual-port RAM with one write
    port and two read ports. Simultaneous read and write
    operations to the same or different addresses are
    supported.
    RAM conguration options are selected by placing the
    appropriate library symbol.
    Choosing a RAM Conguration Mode
    The appropriate choice of RAM mode for a given design
    should be based on timing and resource requirements,
    desired functionality, and the simplicity of the design pro-
    cess. Recommended usage is shown in Table 4.
    The difference between level-sensitive, edge-triggered,
    and dual-port RAM is only in the write operation. Read
    operation and timing is identical for all modes of operation.
    RAM Inputs and Outputs
    The F1-F4 and G1-G4 inputs to the function generators act
    as address lines, selecting a particular memory cell in each
    look-up table.
    The functionality of the CLB control signals changes when
    the function generators are congured as RAM. The
    DIN/H2, H1, and SR/H0 lines become the two data inputs
    (D0, D1) and the Write Enable (WE) input for the 16x2
    memory. When the 32x1 conguration is selected, D1 acts
    as the fth address bit and D0 is the data input.
    The contents of the memory cell(s) being addressed are
    available at the F’ and G’ function-generator outputs. They
    can exit the CLB through its X and Y outputs, or can be cap-
    tured in the CLB ip-op(s).
    Conguring the CLB function generators as Read/Write
    memory does not affect the functionality of the other por-
    Table 3: Supported RAM Modes
    16
    x
    1
    16
    x
    2
    32
    x
    1
    Edge-
    Triggered
    Timing
    Level-
    Sensitive
    Timing
    Single-Port
    √√√
    √
    Dual-Port
    √
    Table 4: RAM Mode Selection
    Level-Sens
    itive
    Edge-Trigg
    ered
    Dual-Port
    Edge-Trigg
    ered
    Use for New
    Designs?
    No
    Yes
    Size (16x1,
    Registered)
    1/2 CLB
    1 CLB
    Simultaneous
    Read/Write
    No
    Yes
    Relative
    Performance
    X2X
    2X (4X
    effective)
    Product Obsolete or Under Obsolescence
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    XC4013XL-3BG256C0568 制造商:Xilinx 功能描述:
    XC4013XL-3BG256I 功能描述:IC FPGA I-TEMP 3.3V 3SPD 256PBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱(chēng):122-1789
    XC4013XL-3BG256M 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
    XC4013XL-3HT144C 功能描述:IC FPGA C-TEMP 3.3V 3SPD 144HQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱(chēng):122-1789
    XC4013XL-3HT144I 功能描述:IC FPGA I-TEMP 3.3V 3SPD 144HQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱(chēng):122-1789
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