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參數(shù)資料
| 型號(hào)： | XC4025E-4HQ304I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 38/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA I-TEMP 5V 4 SPD 304-HQFP |
| 產(chǎn)品變化通告： | XC4000(XL,XLA,E) Discontinuation 15/Nov/2004 |
| 標(biāo)準(zhǔn)包裝： | 12 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 1024 |
| 邏輯元件/單元數(shù)： | 2432 |
| RAM 位總計(jì)： | 32768 |
| 輸入/輸出數(shù)： | 256 |
| 門數(shù)： | 25000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 304-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 304-PQFP（40x40） |
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R
May 14, 1999 (Version 1.6)
6-47
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
is passed through and is captured by each FPGA when it
recognizes the 0010 preamble. Following the length-count
data, each FPGA outputs a High on DOUT until it has
received its required number of data frames.
After an FPGA has received its conguration data, it
passes on any additional frame start bits and conguration
data on DOUT. When the total number of conguration
clocks applied after memory initialization equals the value
of the 24-bit length count, the FPGAs begin the start-up
sequence and become operational together. FPGA I/O are
normally released two CCLK cycles after the last congura-
tion bit is received. Figure 47 on page 53 shows the
start-up timing for an XC4000 Series device.
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The PROM le formatter must
be used to combine the bitstreams for a daisy-chained con-
guration.
Multi-Family Daisy Chain
All Xilinx FPGAs of the XC2000, XC3000, and XC4000
Series use a compatible bitstream format and can, there-
fore, be connected in a daisy chain in an arbitrary
sequence. There is, however, one limitation. The lead
device must belong to the highest family in the chain. If the
chain contains XC4000 Series devices, the master nor-
mally cannot be an XC2000 or XC3000 device.
The reason for this rule is shown in Figure 47 on page 53.
Since all devices in the chain store the same length count
value and generate or receive one common sequence of
CCLK pulses, they all recognize length-count match on the
same CCLK edge, as indicated on the left edge of
Figure 47. The master device then generates additional
CCLK pulses until it reaches its nish point F. The different
families generate or require different numbers of additional
CCLK pulses until they reach F. Not reaching F means that
the device does not really nish its conguration, although
DONE may have gone High, the outputs became active,
and the internal reset was released. For the XC4000 Series
device, not reaching F means that readback cannot be ini-
tiated and most boundary scan instructions cannot be
used.
The user has some control over the relative timing of these
events and can, therefore, make sure that they occur at the
proper time and the nish point F is reached. Timing is con-
trolled using options in the bitstream generation software.
XC3000 Master with an XC4000 Series Slave
Some designers want to use an inexpensive lead device in
peripheral mode and have the more precious I/O pins of the
XC4000 Series devices all available for user I/O. Figure 44
provides a solution for that case.
This solution requires one CLB, one IOB and pin, and an
internal oscillator with a frequency of up to 5 MHz as a
clock source. The XC3000 master device must be cong-
ured with late Internal Reset, which is the default option.
One CLB and one IOB in the lead XC3000-family device
are used to generate the additional CCLK pulse required by
the XC4000 Series devices. When the lead device removes
the internal RESET signal, the 2-bit shift register responds
to its clock input and generates an active Low output signal
for the duration of the subsequent clock period. An external
connection between this output and CCLK thus creates the
extra CCLK pulse.
Output
Connected
to CCLK
OE/T
0
1
0
.
0
1
.
Reset
X5223
etc
Active Low Output
Active High Output
Figure 44: CCLK Generation for XC3000 Master
Driving an XC4000 Series Slave
Product Obsolete or Under Obsolescence
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