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參數(shù)資料
| 型號： | XC4036XL-1HQ304I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 28/68頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA I-TEMP 3.3V 1SPD 304HQFP |
| 產(chǎn)品變化通告： | XC4000(XL,XLA,E) Discontinuation 15/Nov/2004 |
| 標(biāo)準(zhǔn)包裝： | 12 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 1296 |
| 邏輯元件/單元數(shù)： | 3078 |
| RAM 位總計： | 41472 |
| 輸入/輸出數(shù)： | 256 |
| 門數(shù)： | 36000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 304-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 304-PQFP（40x40） |
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-38
May 14, 1999 (Version 1.6)
Global Early Buffers
Each corner of the XC4000X device has two Global Early
buffers. The primary purpose of the Global Early buffers is
to provide an earlier clock access than the potentially
heavily-loaded Global Low-Skew buffers. A clock source
applied to both buffers will result in the Global Early clock
edge occurring several nanoseconds earlier than the Glo-
bal Low-Skew buffer clock edge, due to the lighter loading.
Global Early buffers also facilitate the fast capture of device
inputs, using the Fast Capture latches described in “IOB
Input Signals” on page 20. For Fast Capture, take a single
clock signal, and route it through both a Global Early buffer
and a Global Low-Skew buffer. (The two buffers share an
input pad.) Use the Global Early buffer to clock the Fast
Capture latch, and the Global Low-Skew buffer to clock the
normal input ip-op or latch, as shown in Figure 17 on
The Global Early buffers can also be used to provide a fast
Clock-to-Out on device output pins. However, an early clock
in the output ip-op IOB must be taken into consideration
when calculating the internal clock speed for the design.
The Global Early buffers at the left and right edges of the
chip have slightly different capabilities than the ones at the
top and bottom. Refer to Figure 37, Figure 38, and
Figure 35 on page 36 while reading the following explana-
tion.
Each Global Early buffer can access the eight vertical Glo-
bal lines for all CLBs in the quadrant. Therefore, only
one-fourth of the CLB clock pins can be accessed. This
restriction is in large part responsible for the faster speed of
the buffers, relative to the Global Low-Skew buffers.
The left-side Global Early buffers can each drive two of the
four vertical lines accessing the IOBs on the entire left edge
of the device. The right-side Global Early buffers can each
drive two of the eight vertical lines accessing the IOBs on
the entire right edge of the device. (See Figure 37.)
Each left and right Global Early buffer can also drive half of
the IOBs along either the top or bottom edge of the device,
using a dedicated line that can only be accessed through
the Global Early buffers.
The top and bottom Global Early buffers can drive half of
the IOBs along either the left or right edge of the device, as
shown in Figure 38. They can only access the top and bot-
tom IOBs via the CLB global lines.
16
25
3
8
4
7
CLB
I
O
B
I
O
B
I
O
B
I
O
B
IOB
X6753
Figure 36: Any BUFGLS (GCK1 - GCK8) Can
Drive Any or All Clock Inputs on the Device
16
25
3
8
4
7
CLB
I
O
B
I
O
B
I
O
B
I
O
B
IOB
X6751
Figure 37: Left and Right BUFGEs Can Drive Any or
All Clock Inputs in Same Quadrant or Edge (GCK1 is
shown. GCK2, GCK5 and GCK6 are similar.)
16
25
3
8
4
7
CLB
I
O
B
I
O
B
I
O
B
I
O
B
IOB
X6747
Figure 38: Top and Bottom BUFGEs Can Drive Any
or All Clock Inputs in Same Quadrant (GCK8 is
shown. GCK3, GCK4 and GCK7 are similar.)
Product Obsolete or Under Obsolescence
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