參數(shù)資料
型號: XC4036XL-2BG432C
廠商: Xilinx Inc
文件頁數(shù): 60/68頁
文件大小: 0K
描述: IC FPGA C-TEMP 3.3V 2SPD 432MBGA
產(chǎn)品變化通告: XC4000(XL,XLA,E) Discontinuation 15/Nov/2004
標(biāo)準(zhǔn)包裝: 21
系列: XC4000E/X
LAB/CLB數(shù): 1296
邏輯元件/單元數(shù): 3078
RAM 位總計: 41472
輸入/輸出數(shù): 288
門數(shù): 36000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 432-LBGA,金屬
供應(yīng)商設(shè)備封裝: 432-MBGA(40x40)
R
May 14, 1999 (Version 1.6)
6-67
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics
Previous Byte D6
D7
D0
D1
D2
1
TCA
2
TDC
4
TWTRB
3
TCD
6
TBUSY
READY
BUSY
RS, CS0
WS, CS1
D7
WS/CS0
RS, CS1
D0-D7
CCLK
RDY/BUSY
DOUT
Write to LCA
Read Status
X6097
7
4
Description
Symbol
Min
Max
Units
Write
Effective Write time
(CS0, WS=Low; RS, CS1=High)
1TCA
100
ns
DIN setup time
2
TDC
60
ns
DIN hold time
3
TCD
0ns
RDY
RDY/BUSY delay after end of
Write or Read
4TWTRB
60
ns
RDY/BUSY active after beginning
of Read
760
ns
RDY/BUSY Low output (Note 4)
6
TBUSY
2
9
CCLK
periods
Notes:
1. Conguration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte
processing and the phase of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word
is loaded into the input register before the second-level buffer has started shifting out data
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS.RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Product Obsolete or Under Obsolescence
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XC4036XL-2BG432I 功能描述:IC FPGA I-TEMP 3.3V 2SPD 432MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱:122-1789
XC4036XL-2HQ160C 功能描述:IC FPGA C-TEMP 3.3V 2SPD 160HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱:122-1789
XC4036XL-2HQ160I 功能描述:IC FPGA I-TEMP 3.3V 2SPD 160HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱:122-1789
XC4036XL-2HQ208C 功能描述:IC FPGA C-TEMP 3.3V 2SPD 208HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱:122-1789
XC4036XL-2HQ208I 功能描述:IC FPGA I-TEMP 3.3V 2SPD 208HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱:122-1789