參數(shù)資料
型號(hào)： XC4036XL-2BG432I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 43/68頁(yè)
文件大小： 0K
描述： IC FPGA I-TEMP 3.3V 2SPD 432MBGA
產(chǎn)品變化通告： XC4000(XL,XLA,E) Discontinuation 15/Nov/2004
標(biāo)準(zhǔn)包裝： 21
系列： XC4000E/X
LAB/CLB數(shù)： 1296
邏輯元件/單元數(shù)： 3078
RAM 位總計(jì)： 41472
輸入/輸出數(shù)： 288
門(mén)數(shù)： 36000
電源電壓： 3 V ~ 3.6 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 432-LBGA，金屬
供應(yīng)商設(shè)備封裝： 432-MBGA（40x40）
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-52
May 14, 1999 (Version 1.6)
The default option, and the most practical one, is for DONE
to go High rst, disconnecting the conguration data source
and avoiding any contention when the I/Os become active
one clock later. Reset/Set is then released another clock
period later to make sure that user-operation starts from
stable internal conditions. This is the most common
sequence, shown with heavy lines in Figure 47, but the
designer can modify it to meet particular requirements.
Normally, the start-up sequence is controlled by the internal
device oscillator output (CCLK), which is asynchronous to
the system clock.
XC4000 Series offers another start-up clocking option,
UCLK_NOSYNC. The three events described above need
not be triggered by CCLK. They can, as a conguration
option, be triggered by a user clock. This means that the
device can wake up in synchronism with the user system.
When the UCLK_SYNC option is enabled, the user can
externally hold the open-drain DONE output Low, and thus
stall all further progress in the start-up sequence until
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a com-
mon user clock, or to guarantee that all devices are suc-
cessfully congured before any I/Os go active.
If either of these two options is selected, and no user clock
is specied in the design or attached to the device, the chip
could reach a point where the conguration of the device is
complete and the Done pin is asserted, but the outputs do
not become active. The solution is either to recreate the bit-
stream specifying the start-up clock as CCLK, or to supply
the appropriate user clock.
Start-up Sequence
The Start-up sequence begins when the conguration
memory is full, and the total number of conguration clocks
received since INIT went High equals the loaded value of
the length count.
The next rising clock edge sets a ip-op Q0, shown in
Figure 48. Q0 is the leading bit of a 5-bit shift register. The
outputs of this register can be programmed to control three
events.
The release of the open-drain DONE output
The change of conguration-related pins to the user
function, activating all IOBs.
The termination of the global Set/Reset initialization of
all CLB and IOB storage elements.
The DONE pin can also be wire-ANDed with DONE pins of
other FPGAs or with other external signals, and can then
be used as input to bit Q3 of the start-up register. This is
called “Start-up Timing Synchronous to Done In” and is
selected by either CCLK_SYNC or UCLK_SYNC.
When DONE is not used as an input, the operation is called
“Start-up Timing Not Synchronous to DONE In,” and is
selected by either CCLK_NOSYNC or UCLK_NOSYNC.
As a conguration option, the start-up control register
beyond Q0 can be clocked either by subsequent CCLK
pulses or from an on-chip user net called STARTUP.CLK.
These signals can be accessed by placing the STARTUP
library symbol.
Start-up from CCLK
If CCLK is used to drive the start-up, Q0 through Q3 pro-
vide the timing. Heavy lines in Figure 47 show the default
timing, which is compatible with XC2000 and XC3000
devices using early DONE and late Reset. The thin lines
indicate all other possible timing options.
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
ACC65DRYN CONN EDGECARD 130PS .100 DIP SLD
XC4036XL-2BG432C IC FPGA C-TEMP 3.3V 2SPD 432MBGA
IDT71V35761S183BGI8 IC SRAM 4MBIT 183MHZ 119BGA
ABB120DHLN CONN EDGECARD 240PS .050 DIP SLD
HMM15DREN CONN EDGECARD 30POS .156 EYELET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4036XL-2HQ160C 功能描述:IC FPGA C-TEMP 3.3V 2SPD 160HQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XC4036XL-2HQ160I 功能描述:IC FPGA I-TEMP 3.3V 2SPD 160HQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XC4036XL-2HQ208C 功能描述:IC FPGA C-TEMP 3.3V 2SPD 208HQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XC4036XL-2HQ208I 功能描述:IC FPGA I-TEMP 3.3V 2SPD 208HQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XC4036XL-2HQ240C 功能描述:IC FPGA 1296 CLB'S 240-HQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*