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參數(shù)資料
| 型號： | XC4VLX25-12SFG363C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX-4 LX 25K 363FCBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-4 LX |
| LAB/CLB數(shù)： | 2688 |
| 邏輯元件/單元數(shù)： | 24192 |
| RAM 位總計(jì)： | 1327104 |
| 輸入/輸出數(shù)： | 240 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 363-FBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 363-FCBGA（17x17） |
| 配用： | 807-1004-ND - DAUGHTER CARD WITH VIRTEX-4 122-1523-ND - EVALUATION PLATFORM VIRTEX-4 |
Virtex-4 Family Overview
DS112 (v3.1) August 30, 2010
Product Specification
2
R
System Blocks Common to All Virtex-4 Families
Xesium Clock Technology
Up to twenty Digital Clock Manager (DCM) modules
-
Precision clock deskew and phase shift
-
Flexible frequency synthesis
-
Dual operating modes to ease performance trade-off
decisions
-
Improved maximum input/output frequency
-
Improved phase shifting resolution
-
Reduced output jitter
-
Low-power operation
-
Enhanced phase detectors
-
Wide phase shift range
Companion Phase-Matched Clock Divider (PMCD)
blocks
Differential clocking structure for optimized low-jitter
clocking and precise duty cycle
32 Global Clock networks
Regional I/O and Local clocks
Flexible Logic Resources
Up to 40% speed improvement over previous
generation devices
Up to 200,000 logic cells including:
-
Up to 178,176 internal registers with clock enable
(XC4VLX200)
-
Up to 178,176 look-up tables (LUTs)
-
Logic expanding multiplexers and I/O registers
Cascadable variable shift registers or distributed
memory capability
500 MHz XtremeDSP Slices
Dedicated 18-bit x 18-bit multiplier,
multiply-accumulator, or multiply-adder blocks
Optional pipeline stages for enhanced performance
Optional 48-bit accumulator for multiply accumulate
(MACC) operation
Integrated adder for complex-multiply or multiply-add
operation
Cascadeable Multiply or MACC
Up to 100% speed improvement over previous
generation devices.
500 MHz Integrated Block Memory
Up to 10 Mb of integrated block memory
Optional pipeline stages for higher performance
Multi-rate FIFO support logic
-
Full and Empty Flag support
-
Fully programmable AF and AE Flags
-
Synchronous/ Asynchronous Operation
Dual-port architecture
Independent read and write port width selection (RAM
only)
18 Kbit blocks (memory and parity/sideband memory
support)
Configurations from 16K x 1 to 512 x 36
(4K x 4 to 512 x 36 for FIFO operation)
Byte-write capability (connection to PPC405, etc.)
Dedicated cascade routing to form 32K x 1 memory
without using FPGA routing
Up to 100% speed improvement over previous
generation devices.
XC4VSX25
64 x 40
23,040
10,240
160
128
2,304
4
0
N/A
9
320
XC4VSX35
96 x 40
34,560
15,360
240
192
3,456
8
4
N/A
11
448
XC4VSX55
128 x 48
55,296
24,576
384
512
320
5,760
8
4
N/A
13
640
XC4VFX12
64 x 24
12,312
5,472
86
32
36
648
4
0
1
2
N/A
9
320
XC4VFX20
64 x 36
19,224
8,544
134
32
68
1,224
4
0
1
2
8
9
320
XC4VFX40
96 x 52
41,904
18,624
291
48
144
2,592
8
4
2
4
12
11
448
XC4VFX60
128 x 52
56,880
25,280
395
128
232
4,176
12
8
2
4
16
13
576
XC4VFX100
160 x 68
94,896
42,176
659
160
376
6,768
12
8
2
4
20
15
768
XC4VFX140
192 x 84
142,128
63,168
987
192
552
9,936
20
8
2
4
24
17
896
Notes:
1.
One CLB = Four Slices = Maximum of 64 bits.
2.
Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator
3.
Some of the row/column array is used by the processors in the FX devices.
Table 1: Virtex-4 FPGA Family Members (Continued)
Device
Configurable Logic Blocks (CLBs)(1)
XtremeDSP
Slices(2)
Block RAM
DCMs PMCDs
PowerPC
Processor
Blocks
Ethernet
MACs
RocketIO
Transceiver
Blocks
Total
I/O
Banks
Max
User
I/O
Array(3)
Row x Col
Logic
Cells
Slices
Max
Distributed
RAM (Kb)
18 Kb
Blocks
Max
Block
RAM (Kb)
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