參數(shù)資料
型號(hào): XC5204-5PQ100I
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場(chǎng)可編程門(mén)陣列(FPGA)
文件頁(yè)數(shù): 50/73頁(yè)
文件大?。?/td> 598K
代理商: XC5204-5PQ100I
R
XC5200 Series Field Programmable Gate Arrays
7-132
November 5, 1998 (Version 5.2)
XC5200 Boundary Scan (JTAG) Switching Characteristic Guidelines
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC5200 devices unless otherwise noted.
Speed Grade
Description
Setup and Hold
Input (TDI) to clock (TCK)
setup time
Input (TDI) to clock (TCK)
hold time
Input (TMS) to clock (TCK)
setup time
Input (TMS) to clock (TCK)
hold time
Propagation Delay
Clock (TCK) to Pad (TDO)
Clock
Clock (TCK) High
Clock (TCK) Low
F
MAX
(MHz)
-6
-5
-4
-3
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
T
TDITCK
T
TCKTDI
T
TMSTCK
T
TCKTMS
30.0
0
15.0
0
30.0
0
15.0
0
30.0
0
15.0
0
30.0
0
15.0
0
T
TCKPO
30.0
30.0
30.0
30.0
T
TCKH
T
TCKL
F
MAX
30.0
30.0
30.0
30.0
30.0
30.0
30.0
30.0
10.0
10.0
10.0
10.0
Note 1:
Input pad setup and hold times are specified with respect to the internal clock.
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