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參數(shù)資料
| 型號： | XC5206-5PC84C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 73/73頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 196 CLB'S 84-PLCC |
| 產(chǎn)品變化通告： | XC5200 Discontinuation 27/Aug/2004 |
| 標準包裝： | 15 |
| 系列： | XC5200 |
| LAB/CLB數(shù)： | 196 |
| 邏輯元件/單元數(shù)： | 784 |
| 輸入/輸出數(shù)： | 65 |
| 門數(shù)： | 10000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應商設備封裝： | 84-PLCC |
| 其它名稱： | 122-1138 |
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R
November 5, 1998 (Version 5.2)
7-91
XC5200 Series Field Programmable Gate Arrays
7
Input/Output Blocks
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals.
The I/O block, shown in Figure 11, consists of an input
buffer and an output buffer. The output driver is an 8-mA
full-rail CMOS buffer with 3-state control. Two slew-rate
control modes are supported to minimize bus transients.
Both the output buffer and the 3-state control are invertible.
The input buffer has globally selected CMOS or TTL input
thresholds. The input buffer is invertible and also provides a
programmable delay line to assure reliable chip-to-chip
set-up and hold times. Minimum ESD protection is 3 KV
using the Human Body Model.
IOB Input Signals
The XC5200 inputs can be globally configured for either
TTL (1.2V) or CMOS thresholds, using an option in the bit-
stream generation software. There is a slight hysteresis of
about 300mV.
The inputs of XC5200-Series 5-Volt devices can be driven
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
in TTL mode.
Supported sources for XC5200-Series device inputs are
shown in Table 5.
Optional Delay Guarantees Zero Hold Time
XC5200 devices do not have storage elements in the IOBs.
However, XC5200 IOBs can be efficiently routed to CLB
flip-flops or latches to store the I/O signals.
The data input to the register can optionally be delayed by
several nanoseconds. With the delay enabled, the setup
time of the input flip-flop is increased so that normal clock
routing does not result in a positive hold-time requirement.
A positive hold time requirement can lead to unreliable,
temperature- or processing-dependent operation.
The input flip-flop setup time is defined between the data
measured at the device I/O pin and the clock input at the
CLB (not at the clock pin).
Any routing delay from the
device clock pin to the clock input of the CLB must, there-
fore, be subtracted from this setup time to arrive at the real
setup time requirement relative to the device pins. A short
specified setup time might, therefore, result in a negative
setup time at the device pins, i.e., a positive hold-time
requirement.
When a delay is inserted on the data line, more clock delay
can be tolerated without causing a positive hold-time
requirement. Sufficient delay eliminates the possibility of a
data hold-time requirement at the external pin. The maxi-
mum delay is therefore inserted as the software default.
The XC5200 IOB has a one-tap delay element: either the
delay is inserted (default), or it is not. The delay guarantees
a zero hold time with respect to clocks routed through any
of the XC5200 global clock buffers. (See “Global Lines” on
page 96 for a description of the global clock buffers in the
XC5200.) For a shorter input register setup time, with
D
N
D
C
D
B
D
A
AB
C
N
Z = D
A
A + D
B
B + D
C
C + D
N
N
~100 k
"Weak Keeper"
X6466
BUFT
Figure 10: 3-State Buffers Implement a Multiplexer
Figure 11: XC5200 I/O Block
I
O
T
PAD
Vcc
X9001
Input
Buffer
Delay
Pullup
Pulldown
Slew Rate
Control
Output
Buffer
Table 5: Supported Sources for XC5200-Series Device
Inputs
Source
XC5200 Input Mode
5 V,
TTL
5 V,
CMOS
Any device, Vcc = 3.3 V,
CMOS outputs
√
Unreliable
Data
Any device, Vcc = 5 V,
TTL outputs
√
Any device, Vcc = 5 V,
CMOS outputs
√√
Product Obsolete or Under Obsolescence
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