參數(shù)資料
型號(hào): XC5206-5PQ208C
廠商: Xilinx Inc
文件頁數(shù): 46/73頁
文件大?。?/td> 0K
描述: IC FPGA 196 CLB'S 208-PQFP
產(chǎn)品變化通告: XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝: 24
系列: XC5200
LAB/CLB數(shù): 196
邏輯元件/單元數(shù): 784
輸入/輸出數(shù): 148
門數(shù): 10000
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
其它名稱: 122-1142
R
XC5200 Series Field Programmable Gate Arrays
7-132
November 5, 1998 (Version 5.2)
XC5200 Boundary Scan (JTAG) Switching Characteristic Guidelines
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC5200 devices unless otherwise noted.
Speed Grade
-6
-5
-4
-3
Description
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Setup and Hold
Input (TDI) to clock (TCK)
setup time
Input (TDI) to clock (TCK)
hold time
Input (TMS) to clock (TCK)
setup time
Input (TMS) to clock (TCK)
hold time
TTDITCK
TTCKTDI
TTMSTCK
TTCKTMS
30.0
0
15.0
0
30.0
0
15.0
0
30.0
0
15.0
0
30.0
0
15.0
0
Propagation Delay
Clock (TCK) to Pad (TDO)
TTCKPO
30.0
Clock
Clock (TCK) High
Clock (TCK) Low
TTCKH
TTCKL
30.0
FMAX (MHz)
FMAX
10.0
Note 1:
Input pad setup and hold times are specified with respect to the internal clock.
Product Obsolete or Under Obsolescence
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