參數(shù)資料
型號(hào)： XC5210-5PQ160I
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（FPGA）
文件頁(yè)數(shù)： 12/73頁(yè)
文件大小： 598K
代理商： XC5210-5PQ160I
R
XC5200 Series Field Programmable Gate Arrays
7-94
November 5, 1998 (Version 5.2)
CLB inputs have several possible sources: the 24 signals
from the GRM, 16 direct connections from neighboring
VersaBlocks, four signals from global, low-skew buffers,
and the four signals from the CLB output multiplexers.
Unlike the output multiplexers, the input multiplexers are
not fully populated; i.e., only a subset of the available sig-
nals can be connected to a given CLB input. The flexibility
of LUT input swapping and LUT mapping compensates for
this limitation. For example, if a 2-input NAND gate is
required, it can be mapped into any of the four LUTs, and
use any two of the four inputs to the LUT.
Direct Connects
The unidirectional direct-connect segments are connected
to the logic input/output pins through the CLB input and out-
put multiplexer arrays, and thus bypass the general routing
matrix altogether. These lines increase the routing channel
utilization, while simultaneously reducing the delay
incurred in speed-critical connections.
The direct connects also provide a high-speed path from
the edge CLBs to the VersaRing input/output buffers, and
thus reduce pin-to-pin set-up time, clock-to-out, and combi-
national propagation delay. Direct connects from the input
buffers to the CLB DI pin (direct flip-flop input) are only
available on the left and right edges of the device. CLB
look-up table inputs and combinatorial/registered outputs
have direct connects to input/output buffers on all four
sides.
The direct connects are ideal for developing customized
RPM cells. Using direct connects improves the macro per-
formance, and leaves the other routing channels intact for
improved routing. Direct connects can also route through a
CLB using one of the four cell-feedthrough paths.
General Routing Matrix
The General Routing Matrix, shown in
Figure 15
, provides
flexible bidirectional connections to the Local Interconnect
Figure 14: VersaBlock Details
4
4
4
4
5
5
5
5
3
3
3
3
24
To GRM
M0-M23
CLB
CLK
CE
Direct North
Direct to
East
To
Longlines
and GRM
TQ0-TQ3
Global Nets
Feedback
Direct West
Direct South
CLR
C
IN
C
OUT
V
CC
/GND
TS
4
4
North
4
8
South
4
East
4
West
4
LC3
LC2
LC1
LC0
Output
Multiplexers
Input
Multiplexers
8
4
4
4
X5724
相關(guān)PDF資料
PDF描述
XC5210-5PQ208I Field Programmable Gate Array (FPGA)
XC5210-5PQ240I Field Programmable Gate Array (FPGA)
XC5210-6PQ160I Field Programmable Gate Array (FPGA)
XC5210-6PQ208I Field Programmable Gate Array (FPGA)
XC5210-6PQ240I Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC5210-5PQ208C 功能描述:IC FPGA 324 CLB'S 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC5200 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC5210-5PQ208I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
XC5210-5PQ240C 功能描述:IC FPGA 324 CLB'S 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC5200 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC5210-5PQ240C0167 制造商:Xilinx 功能描述:
XC5210-5PQ240I 制造商:Xilinx 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*