參數(shù)資料
型號(hào): XC5210-5PQ208I
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場(chǎng)可編程門(mén)陣列(FPGA)
文件頁(yè)數(shù): 35/73頁(yè)
文件大小: 598K
代理商: XC5210-5PQ208I
R
November 5, 1998 (Version 5.2)
7-117
XC5200 Series Field Programmable Gate Arrays
7
.
Note:
1. At power-up, V
must rise from 2.0 V to V
CC
min in less then 25 ms, otherwise delay configuration by pulling PROGRAM
Low until V
is Valid.
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 32: Master Parallel Mode Programming Switching Characteristics
Address for Byte n
Byte
2 T
DRC
Address for Byte n + 1
D7
D6
A0-A17
(output)
D0-D7
RCLK
(output)
CCLK
(output)
DOUT
(output)
1 T
RAC
7 CCLKs
CCLK
3 T
RCD
Byte n - 1
X6078
Description
Symbol
Min
0
60
0
Max
200
Units
ns
ns
ns
CCLK
Delay to Address valid
Data setup time
Data hold time
1
2
3
T
RAC
T
DRC
T
RCD
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XC5210-5PQ240C 功能描述:IC FPGA 324 CLB'S 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門(mén)陣列) 系列:XC5200 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
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