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參數(shù)資料
| 型號： | XC5210-6PQ160I |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 46/73頁 |
| 文件大小： | 598K |
| 代理商： | XC5210-6PQ160I |
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R
XC5200 Series Field Programmable Gate Arrays
7-128
November 5, 1998 (Version 5.2)
XC5200 Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
XC5200 Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade
-6
-5
-4
-3
Description
Symbol
Device
Max
(ns)
9.1
9.3
9.4
9.4
10.5
Max
(ns)
8.5
8.7
8.8
8.8
9.9
Max
(ns)
8.0
8.2
8.3
8.5
9.8
Max
(ns)
6.9
7.6
7.7
7.7
9.6
Global Signal Distribution
From pad through global buffer, to any clock (CK)
T
BUFG
XC5202
XC5204
XC5206
XC5210
XC5215
Speed Grade
-6
-5
-4
-3
Description
Symbol
Device
Max
(ns)
6.0
6.4
6.6
6.6
7.3
Max
(ns)
3.8
4.1
4.2
4.2
4.6
Max
(ns)
3.0
3.2
3.3
3.3
3.8
Max
(ns)
2.0
2.3
2.7
2.9
3.2
TBUF driving a Longline
TS
I
TBUF
I to Longline, while TS is Low; i.e., buffer is constantly ac-
tive
TS going Low to Longline going from floating High or Low
to active Low or High
T
IO
XC5202
XC5204
XC5206
XC5210
XC5215
T
ON
XC5202
XC5204
XC5206
XC5210
XC5215
XC52xx
7.8
8.3
8.4
8.4
8.9
3.0
5.6
5.9
6.0
6.0
6.3
2.8
4.7
4.9
5.0
5.0
5.3
2.6
4.0
4.3
4.4
4.4
4.5
2.4
TS going High to TBUF going inactive, not driving
Longline
Note:
1. Die-size-dependent parameters are based upon XC5215 characterization. Production specifications will vary with array
size.
T
OFF
O
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| XC5210-6PQ208C | 功能描述:IC FPGA 324 CLB'S 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC5200 產品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
| XC5210-6PQ208C0167 | 制造商:Xilinx 功能描述: |
| XC5210-6PQ208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC5210-6PQ240C | 功能描述:IC FPGA 324 CLB'S 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC5200 產品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
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