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參數(shù)資料
| 型號： | XC5215-4PQ160I |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 12/73頁 |
| 文件大?。?/td> | 598K |
| 代理商： | XC5215-4PQ160I |
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R
XC5200 Series Field Programmable Gate Arrays
7-94
November 5, 1998 (Version 5.2)
CLB inputs have several possible sources: the 24 signals
from the GRM, 16 direct connections from neighboring
VersaBlocks, four signals from global, low-skew buffers,
and the four signals from the CLB output multiplexers.
Unlike the output multiplexers, the input multiplexers are
not fully populated; i.e., only a subset of the available sig-
nals can be connected to a given CLB input. The flexibility
of LUT input swapping and LUT mapping compensates for
this limitation. For example, if a 2-input NAND gate is
required, it can be mapped into any of the four LUTs, and
use any two of the four inputs to the LUT.
Direct Connects
The unidirectional direct-connect segments are connected
to the logic input/output pins through the CLB input and out-
put multiplexer arrays, and thus bypass the general routing
matrix altogether. These lines increase the routing channel
utilization, while simultaneously reducing the delay
incurred in speed-critical connections.
The direct connects also provide a high-speed path from
the edge CLBs to the VersaRing input/output buffers, and
thus reduce pin-to-pin set-up time, clock-to-out, and combi-
national propagation delay. Direct connects from the input
buffers to the CLB DI pin (direct flip-flop input) are only
available on the left and right edges of the device. CLB
look-up table inputs and combinatorial/registered outputs
have direct connects to input/output buffers on all four
sides.
The direct connects are ideal for developing customized
RPM cells. Using direct connects improves the macro per-
formance, and leaves the other routing channels intact for
improved routing. Direct connects can also route through a
CLB using one of the four cell-feedthrough paths.
General Routing Matrix
The General Routing Matrix, shown in
Figure 15
, provides
flexible bidirectional connections to the Local Interconnect
Figure 14: VersaBlock Details
4
4
4
4
5
5
5
5
3
3
3
3
24
To GRM
M0-M23
CLB
CLK
CE
Direct North
Direct to
East
To
Longlines
and GRM
TQ0-TQ3
Global Nets
Feedback
Direct West
Direct South
CLR
C
IN
C
OUT
V
CC
/GND
TS
4
4
North
4
8
South
4
East
4
West
4
LC3
LC2
LC1
LC0
Output
Multiplexers
Input
Multiplexers
8
4
4
4
X5724
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